XC3S400-4FT256C Xilinx Inc, XC3S400-4FT256C Datasheet - Page 112

• Manufacturer Part Number: XC3S400-4FT256C
• Description: SEMI CONDUCTOR
• Manufacturer: Xilinx Inc

Specifications of XC3S400-4FT256C

• Case: BGA
• Dc: 04+

Spartan-3 FPGA Family: Pinout Descriptions
.
Table 76: JTAG Pin Descriptions
JTAG: Dedicated JTAG Port Pins
These pins are dedicated connections to the four-wire IEEE
1532/IEEE 1149.1 JTAG port, shown in
described in
ary-scan testing, device configuration, application debug-
ging, and possibly an additional serial port for the
application. These pins are dedicated and are not available
as user-I/O pins. Every package has four dedicated JTAG
pins and these pins are powered by the +2.5V VCCAUX
supply.
For additional information on JTAG configuration, see
Boundary-Scan (JTAG) Mode, page
IDCODE Register
Spartan-3 FPGAs contain a 32-bit identification register
called the IDCODE register, as defined in the IEEE 1149.1
JTAG standard. The fixed value electrically identifies the
manufacture (Xilinx) and the type of device being addressed
over a JTAG chain. This register allows the JTAG host to
identify the device being tested or programmed via JTAG.
112
TCK
TDI
TMS
TDO
Pin Name
TDI
TMS
TCK
Table
Input
Input
Input
Output
Direction
Data In
Mode Select
Figure 41: JTAG Port
Clock
76. The JTAG port is used for bound-
JTAG Port
Test Clock: The TCK clock signal synchronizes all
boundary scan operations on its rising edge.
Test Data Input: TDI is the serial data input for all JTAG
instruction and data registers. This input is sampled on
the rising edge of TCK.
Test Mode Select: The TMS input controls the
sequence of states through which the JTAG TAP state
machine passes. This input is sampled on the rising
edge of TCK.
Test Data Output: The TDO pin is the data output for
all JTAG instruction and data registers. This output is
sampled on the rising edge of TCK. The TDO output is
an active totem-pole driver and is not like the
open-collector TDO output on Virtex™-II Pro FPGAs.
Data Out
49.
Figure 41
DS099-4_04_042103
Description
TDO
www.xilinx.com
and
Table 77: Spartan-3 JTAG IDCODE Register Values
(hexadecimal)
Using JTAG Port After Configuration
The JTAG port is always active and available before, during,
and after FPGA configuration. Add the BSCAN_SPARTAN3
primitive to the design to create user-defined JTAG instruc-
tions and JTAG chains to communicate with internal logic.
Furthermore, the contents of the User ID register within the
JTAG port can be specified as a Bitstream Generation
option. By default, the 32-bit User ID register contains
0xFFFFFFFF.
Precautions When Using the JTAG Port in 3.3V
Environments
The JTAG port is powered by the +2.5V VCCAUX power
supply. When connecting to a 3.3V interface, the JTAG input
pins must be current-limited using a series resistor. Simi-
larly, the TDO pin is a CMOS output powered from +2.5V.
XC3S50
XC3S200
XC3S400
XC3S1000
XC3S1500
XC3S2000
XC3S4000
XC3S5000
Part Number
The BitGen option TckPin
determines whether a pull-up
resistor, pull-down resistor or no
resistor is present.
The BitGen option TdiPin
determines whether a pull-up
resistor, pull-down resistor or no
resistor is present.
The BitGen option TmsPin
determines whether a pull-up
resistor, pull-down resistor or no
resistor is present.
The BitGen option TdoPin
determines whether a pull-up
resistor, pull-down resistor or no
resistor is present.
Bitstream Generation Option
IDCODE Register
DS099-4 (v2.2) May 25, 2007
0x0140C093
0x0141C093
0x01414093
0x01428093
0x01434093
0x01440093
0x01448093
0x01450093
Product Specification
R