XC3S400-4FT256C Xilinx Inc, XC3S400-4FT256C Datasheet - Page 115

• Manufacturer Part Number: XC3S400-4FT256C
• Description: SEMI CONDUCTOR
• Manufacturer: Xilinx Inc

Specifications of XC3S400-4FT256C

• Case: BGA
• Dc: 04+

Table 78: Pin Behavior After Power-Up, During Configuration (Continued)
DS099-4 (v2.2) May 25, 2007
Product Specification
IO_Lxxy_#/
D5
IO_Lxxy_#/
D6
IO_Lxxy_#/
D7
IO_Lxxy_#/
CS_B
IO_Lxxy_#/
RDWR_B
IO_Lxxy_#/
BUSY/DOUT
DUAL: Dual-purpose configuration pins (INIT_B has a pull-up resistor to VCCO_4 or VCCO_BOTTOM always active
during configuration, regardless of HSWAP_EN pin)
IO_Lxxy_#/
INIT_B
DCI: Digitally Controlled Impedance reference resistor input pins
IO_Lxxy_#/
VRN_#
IO/VRN_#
IO_Lxxy_#/
VRP_#
IO/VRP_#
GCLK: Global clock buffer inputs
IO_Lxxy_#/
GCLK0 through
GCLK7
VREF: I/O bank input reference voltage pins
IO_Lxxy_#/
VREF_#
IO/VREF_#
CONFIG: Dedicated configuration pins (pull-up resistor to VCCAUX always active during configuration, regardless of
HSWAP_EN pin)
CCLK
PROG_B
DONE
M2
Pin Name
R
INIT_B (I/OD)
DONE (I/OD)
PROG_B (I)
CCLK (I/O)
DOUT (O)
(pull-up)
M2=0 (I)
<0:0:0>
Master
Serial Modes
INIT_B (I/OD)
DONE (I/OD)
PROG_B (I)
Configuration Mode Settings <M2:M1:M0>
DOUT (O)
CCLK (I)
(pull-up)
M2=1 (I)
<1:1:1>
Slave
www.xilinx.com
INIT_B (I/OD)
DONE (I/OD)
RDWR_B (I)
PROG_B (I)
CCLK (I/O)
SelectMap Parallel Modes
BUSY (O)
CS_B (I)
(pull-up)
M2=0 (I)
D5 (I/O)
D6 (I/O)
D7 (I/O)
<0:1:1>
Master
INIT_B (I/OD)
DONE (I/OD)
RDWR_B (I)
PROG_B (I)
BUSY (O)
CS_B (I)
CCLK (I)
(pull-up)
M2=1 (I)
D5 (I/O)
D6 (I/O)
D7 (I/O)
<1:1:0>
Spartan-3 FPGA Family: Pinout Descriptions
Slave
Via JPROG_B
DONE (I/OD)
PROG_B (I),
JTAG Mode
instruction
M2=1 (I)
<1:0:1>
Configuration
ConfigRate
UnusedPin
UnusedPin
UnusedPin
UnusedPin
UnusedPin
UnusedPin
UnusedPin
UnusedPin
UnusedPin
UnusedPin
UnusedPin
UnusedPin
UnusedPin
UnusedPin
DriveDone
Bitstream
DonePipe
DonePin
ProgPin
CclkPin
Option
Persist
Persist
Persist
Persist
Persist
Persist
M2Pin
115