XC3S400-4FT256C Xilinx Inc, XC3S400-4FT256C Datasheet - Page 97

• Manufacturer Part Number: XC3S400-4FT256C
• Description: SEMI CONDUCTOR
• Manufacturer: Xilinx Inc

Specifications of XC3S400-4FT256C

• Case: BGA
• Dc: 04+

Revision History
DS099-3 (v2.2) May 25, 2007
Product Specification
98
02/06/04
03/04/04
08/24/04
12/17/04
08/19/05
04/11/03
07/11/03
Date
R
Version No.
1.0
1.1
1.2
1.3
1.4
1.5
1.6
Initial Xilinx release.
Extended Absolute Maximum Rating for junction temperature in
supply current
Revised V
(Table
numbers
LVPECL standards
Added timing numbers from v1.29 speed files as well as DCM timing
Added reference to errata documents on
information
(Table
(Table
Added note limiting V
differential standards
Table 47
latest characterization data
(Table
specification
Centered_x#_y# is not necessary for Variable Phase Shift mode, removed BitGen command table and
referring text. Adjusted maximum CCLK frequency for the slave serial and parallel configuration modes
(Table
Updated timing parameters to match v1.35 speed file. Improved V
Added a note limiting the rate of change of V
XC3S2000, XC3S4000, and XC3S5000
(Table
FT and FG packages
bitstreams
Table
Updated timing parameters to match v1.37 speed file. All Spartan-3 part types, except XC3S5000, promoted
to Production status. Removed V
(Table
worst-case quiescent current values for XC3S2000, XC3S4000, XC3S5000
temperature range specification and improved typical quiescent current values
minimum clock input frequency specification from 24 MHz down to 18 MHz
minimum and maximum clock output frequency specifications
DCM specifications
Simultaneously Switching Output Guidelines
SSTL18_II I/O standard and timing to support DDR2 SDRAM interfaces. Added differential (or complementary
single-ended) DIFF_HSTL_II_18 and DIFF_SSTL2_II I/O standards, including DCI terminated versions. Added
electro-static discharge (ESD) data for the XC3S2000 and larger FPGAs
errata notices and how to receive automatic notifications of data sheet or errata changes.
43,
32), and differential output voltage levels
32). Updated quiescent current numbers and added information on power-on and surplus current
33). Adjusted V
57). Recommended use of Virtex-II Jitter calculator
65). Inverted CCLK waveform
35). Added SSO guidelines for the VQ, TQ, and PQ packages as well as edited SSO guidelines for the
29). Added equivalent resistance values for internal pull-up and pull-down resistors
and
(Table
Table
IN
(Table 65
(Table
maximum rating
(Table
Table 50
(Table
46,
33). Updated pull-up and pull-down resistor strengths
27). Explained V
Table
(Table 36
61). Changed Phase Shifter lock time parameter
(Table
and
TT
(Table
33) and DLL timing.
REF
(Table
through
range for SSTL2_II signal standards
Table
47, and
range for HSTL_III and HSTL_I_18 and changed V
63), primarily affecting Industrial temperature range applications. Updated
(Table 57
37). Updated Switching Characteristics with speed file v1.32
49). Added maximum CCLK frequencies for configuration using compressed
www.xilinx.com
(Table
and
Table
66). Added specifications for the HSLVDCI standards
CCO
Table
Table
CCO
Spartan-3 FPGA Family: DC and Switching Characteristics
27). Added power-on requirements
55). Corrected IOB test conditions
(Figure
through
ramp rate restriction from all mask revision ‘E’ and later devices
ramp time measurement
(Table
49).
37). Changed CCLK setup time
page
CCAUX
35). Adjusted JTAG setup times
Table
33). Increased I
55. Clarified Absolute Maximum Ratings and added ESD
Description
(Table
and
(Table
61). Improved DCM CLKIN pulse width specification
Table 49
37) for Rev. 0. Published new quiescent current
(Table
31). Added typical quiescent current values for the
(Table
(Table
OH
for QFP packages. Added information on
Table
(Table
60). Improved DCM PSCLK pulse width
and I
CCO
35). Calculated V
59,
(Table
27. Added numbers for typical quiescent
(Table 57
(Table
OL
ramp time specification
(Table
(Table
29). Clarified I
Table
(Table 65
for SSTL2-I and SSTL2-II standards
(Table
(Table
62). Because the BitGen option
IH
(Table
32). Added LVDCI_DV2 and
(Table
60). Added new miscellaneous
min for LVCMOS12
40). Updated DCM timing with
29), leakage current number
(Table
through
27). Added link to Spartan-3
and
57). Improved the DFS
33). Added industrial
67).
OH
(Table
33). Improved the DLL
L
Table
Table
specification
and V
(Table 39
(Table
34,
66).
62).
(Table
OL
Table
32). Added
levels for
(Table
through
29).
35,
34).
97