XC3S400-4FT256C Xilinx Inc, XC3S400-4FT256C Datasheet - Page 113

• Manufacturer Part Number: XC3S400-4FT256C
• Description: SEMI CONDUCTOR
• Manufacturer: Xilinx Inc

Specifications of XC3S400-4FT256C

• Case: BGA
• Dc: 04+

The TDO output can directly drive a 3.3V input but with
reduced noise immunity. See
Interface, page 46
Spartan-3 FPGAs
The following interface precautions are recommended when
connecting the JTAG port to a 3.3V interface.
1. Avoid actively driving the JTAG input signals High with
2. If possible, drive the FPGA JTAG inputs with drivers that
VREF: User I/O or Input Buffer Reference
Voltage for Special Interface Standards
These pins are individual user-I/O pins unless collectively
they supply an input reference voltage, VREF_#, for any
SSTL, HSTL, GTL, or GTLP I/Os implemented in the asso-
ciated I/O bank.
The ‘#’ character in the pin name represents an integer, 0
through 7, that indicates the associated I/O bank.
The VREF function becomes active for this pin whenever a
signal standard requiring a reference voltage is used in the
associated bank.
If used as a user I/O, then each pin behaves as an indepen-
dent I/O described in the I/O type section. If used for a ref-
erence voltage within a bank, then all VREF pins within the
bank must be connected to the same reference voltage.
Spartan-3 devices are designed and characterized to sup-
port certain I/O standards when VREF is connected to
+1.25V, +1.10V, +1.00V, +0.90V, +0.80V, and +0.75V.
During configuration, the VREF pins behave exactly like
user-I/O pins.
If designing for footprint compatibility across the range of
devices in a specific package, and if the VREF_# pins within
a bank connect to an input reference voltage, then also con-
nect any N.C. (not connected) pins on the smaller devices in
that package to the input reference voltage. More details are
provided later for each package type.
N.C. Type: Unconnected Package Pins
Pins marked as “N.C.” are unconnected for the specific
device/package combination. For other devices in this same
package, this pin may be used as an I/O or VREF connec-
DS099-4 (v2.2) May 25, 2007
Product Specification
3.3V signal levels. If required in the application, use
series current-limiting resistors to keep the current
below 10 mA per pin.
can be placed in high-impedance (Hi-Z) after using the
JTAG port. Alternatively, drive the FPGA JTAG inputs
with open-drain outputs, which only drive Low. In both
cases, pull-up resistors are required. The FPGA JTAG
pins have pull-up resistors to VCCAUX before
configuration and optional pull-up resistors after
configuration, controlled by
page
117.
R
for additional details.
or
XAPP453: The 3.3V Configuration of
3.3V-Tolerant Configuration
Bitstream Options,
www.xilinx.com
tion. In both the pinout tables and the footprint diagrams,
unconnected pins are noted with either a black diamond
symbol ( ) or a black square symbol ( ).
If designing for footprint compatibility across multiple device
densities, check the pin types of the other Spartan-3
devices available in the same footprint. If the N.C. pin
matches to VREF pins in other devices, and the VREF pins
are used in the associated I/O bank, then connect the N.C.
to the VREF voltage source.
VCCO Type: Output Voltage Supply for I/O
Bank
Each I/O bank has its own set of voltage supply pins that
determines the output voltage for the output buffers in the
I/O bank. Furthermore, for some I/O standards such as
LVCMOS, LVCMOS25, LVTTL, etc., VCCO sets the input
threshold voltage on the associated input buffers.
Spartan-3 devices are designed and characterized to sup-
port various I/O standards for VCCO values of +1.2V, +1.5V,
+1.8V, +2.5V, and +3.3V.
Most VCCO pins are labeled as VCCO_# where the ‘#’
symbol represents the associated I/O bank number, an inte-
ger ranging from 0 to 7. In the 144-pin TQFP package
(TQ144) however, the VCCO pins along an edge of the
device are combined into a single VCCO input. For exam-
ple, the VCCO inputs for Bank 0 and Bank 1 along the top
edge of the package are combined and relabeled
VCCO_TOP. The bottom, left, and right edges are similarly
combined.
In Serial configuration mode, VCCO_4 must be at a level
compatible with the attached configuration memory or data
source. In Parallel configuration mode, both VCCO_4 and
VCCO_5 must be at the same compatible voltage level.
All VCCO inputs to a bank must be connected together and
to the voltage supply. Furthermore, there must be sufficient
supply decoupling to guarantee problem-free operation, as
described in
Design: Using Bypass/Decoupling Capacitors
VCCINT Type: Voltage Supply for Internal
Core Logic
Internal core logic circuits such as the configurable logic
blocks (CLBs) and programmable interconnect operate
from the VCCINT voltage supply inputs. VCCINT must be
+1.2V.
All VCCINT inputs must be connected together and to the
+1.2V voltage supply. Furthermore, there must be sufficient
supply decoupling to guarantee problem-free operation, as
described in
Design: Using Bypass/Decoupling Capacitors
Spartan-3 FPGA Family: Pinout Descriptions
XAPP623: Power Distribution System (PDS)
XAPP623: Power Distribution System (PDS)
.
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