XC3S400-4FT256C Xilinx Inc, XC3S400-4FT256C Datasheet - Page 4

• Manufacturer Part Number: XC3S400-4FT256C
• Description: SEMI CONDUCTOR
• Manufacturer: Xilinx Inc

Specifications of XC3S400-4FT256C

• Case: BGA
• Dc: 04+

Spartan-3 FPGA Family: Introduction and Ordering Information
Architectural Overview
The Spartan-3 family architecture consists of five funda-
mental programmable functional elements:
•
•
•
4
10
Configurable Logic Blocks (CLBs) contain RAM-based
Look-Up Tables (LUTs) to implement logic and storage
elements that can be used as flip-flops or latches.
CLBs can be programmed to perform a wide variety of
logical functions as well as to store data.
Input/Output Blocks (IOBs) control the flow of data
between the I/O pins and the internal logic of the
device. Each IOB supports bidirectional data flow plus
3-state
standards, including eight high-performance differential
standards, are available as shown in
Data-Rate (DDR) registers are included. The Digitally
Controlled
automatic on-chip terminations, simplifying board
designs.
Block RAM provides data storage in the form of 18-Kbit
dual-port blocks.
operation.
Impedance
Notes:
1.
The two additional block RAM columns of the XC3S4000 and XC3S5000
devices are shown with dashed lines. The XC3S50 has only the block RAM
column on the far left.
Twenty-six
(DCI)
Figure 1: Spartan-3 Family Architecture
feature
different
Table
2. Double
provides
signal
www.xilinx.com
•
•
These elements are organized as shown in
of IOBs surrounds a regular array of CLBs. The XC3S50
has a single column of block RAM embedded in the array.
Those devices ranging from the XC3S200 to the XC3S2000
have two columns of block RAM. The XC3S4000 and
XC3S5000 devices have four RAM columns. Each column
is made up of several 18-Kbit RAM blocks; each block is
associated with a dedicated multiplier. The DCMs are posi-
tioned at the ends of the outer block RAM columns.
The Spartan-3 family features a rich network of traces and
switches that interconnect all five functional elements,
transmitting signals among them. Each functional element
has an associated switch matrix that permits multiple con-
nections to the routing.
Multiplier blocks accept two 18-bit binary numbers as
inputs and calculate the product.
Digital
self-calibrating, fully digital solutions for distributing,
delaying, multiplying, dividing, and phase shifting clock
signals.
Clock
Manager
DS099-1_01_032703
DS099-1 (v2.2) May 25, 2007
(DCM)
Product Specification
blocks
Figure
1. A ring
provide
R