XC3S400-4FT256C Xilinx Inc, XC3S400-4FT256C Datasheet - Page 53

• Manufacturer Part Number: XC3S400-4FT256C
• Description: SEMI CONDUCTOR
• Manufacturer: Xilinx Inc

Specifications of XC3S400-4FT256C

• Case: BGA
• Dc: 04+

threshold levels (see
supplies reach their respective threshold, the POR reset is
released and the FPGA begins its configuration process.
Because the three supply inputs must be valid to release
the POR reset and can be supplied in any order, there are
no specific voltage sequencing requirements. However,
applying the FPGA’s V
ply uses the least I
Once all three supplies are valid, the minimum current
required to power-on the FPGA is equal to the worst-case
quiescent current, as specified in
tan-3 FPGAs do not require Power-On Surge (POS) current
to successfully configure.
Surplus I
If the V
the FPGA may draw a surplus I
the I
The momentary additional I
few hundred milliamperes under nominal conditions, signif-
icantly less than the instantaneous current consumed by the
bypass capacitors at power-on. However, the surplus cur-
rent immediately disappears when the V
applied, and, in response, the FPGA’s I
rent demand drops to the levels specified in
FPGA does not use nor does it require the surplus current
to successfully power-on and configure. If applying V
before V
foldback feature that could inadvertently shut down in the
presence of the surplus current.
Maximum Allowed V
Devices, if V
Early Spartan-3 FPGAs were produced at a 200 mm wafer
production facility and are identified by a fabrication/pro-
cess code of "FQ" on the device top marking, as shown in
Package Marking, page
maximum V
V
V
as T
Spartan-3 FPGAs ordered with SCD0961 are specially
screened to eliminate this V
devices with a mask revision code ‘E’ or later also do not
have this V
devices can be ordered with an SCD0974 code. These
devices are standard Spartan-3 product offerings starting
August 1, 2005 (see
Minimum Allowed V
Devices
Initial Spartan-3 FPGA mask revisions have a limit on how
fast the V
DS099-2 (v2.2) May 25, 2007
Product Specification
CCINT
CCO
CCINT
CCINT
Bank 4 supplies. This maximum ramp rate appears
CCINT
is the last supply to ramp, after the V
CCAUX
in
CCINT
CCO
quiescent current levels specified in
CCINT
R
CCINT
Table 29, page
supply is applied before the V
VCCINT
, ensure that the regulator does not have a
supply can ramp. The minimum allowed
if V
ramp rate requirement. Mask revision ‘E’
CCINT
ramp rate requirement if and only if
XCN05009
CCINT
Supply is Last in Sequence
CCAUX
Table 28, page
CCINT
current.
CCO
7. These "FQ" devices have a
CCINT
CCINT
Applied before V
57.
supply before the V
Ramp Rate on Early
).
CCINT
Ramp Rate on Early
surplus current might be a
ramp rate requirement. All
Table 33, page
current in addition to
CCINT
56). After all three
CCAUX
CCAUX
quiescent cur-
Table
CCAUX
CCAUX
CCINT
60. Spar-
Table
supply is
33. The
supply,
CCINT
www.xilinx.com
sup-
and
33.
-
V
minimum rate is affected by the package inductance. Con-
sequently, the ball grid array and chip-scale packages
(CP132, FT256, FG456, FG676, and FG900) allow a faster
ramp rate than the quad-flat packages (VQ100, TQ144, and
PQ208).
Later devices essentially have no V
again shown in
with a mask revision code ‘E’ or later do not have a V
ramp rate limit. These devices are standard Spartan-3 prod-
uct offerings starting August 1, 2005 (see
Configuration Data Retention, Brown-Out
The FPGA’s configuration data is stored in robust CMOS
configuration latches. The data in these latches is retained
even when the voltages drop to the minimum levels neces-
sary to preserve RAM contents. This is specified in
Table 30, page
If, after configuration, the V
below its data retention voltage, clear the current device
configuration using one of the following methods:
•
•
The POR circuit does not monitor the VCCO_4 supply after
configuration. Consequently, dropping the VCCO_4 voltage
does not reset the device by triggering a Power-On Reset
(POR) event.
No Internal Charge Pumps or Free-Running
Oscillators
Some system applications are sensitive to sources of ana-
log noise. Spartan-3 FPGA circuitry is fully static and does
not employ internal charge pumps.
The CCLK configuration clock is active during the FPGA
configuration process. After configuration completes, the
CCLK oscillator is automatically disabled unless the Bit-
stream Generator (BitGen) option Persist=Yes. See Mod-
ule 4:
Spartan-3 FPGAs optionally support a featured called
tally Controlled Impedance
cation, the DCI logic uses an internal oscillator. The DCI
logic is only enabled if the FPGA application specifies an
I/O standard that requires DCI (LVDCI_33, LVDCI_25, etc.).
If DCI is not used, the associated internal oscillator is also
disabled.
In summary, unless an application uses the Persist=Yes
option or specifies a DCI I/O standard, an FPGA with no
external switching remains fully static.
CCO
Force the V
minimum Power On Reset (POR) voltage threshold
Table 28, page
Assert PROG_B Low.
ramp rate appears as T
Table 79, page
Spartan-3 FPGA Family: Functional Description
57.
CCAUX
Table 29, page
56).
117.
or V
CCINT
CCAUX
CCO
(DCI). When used in an appli-
supply voltage below the
57. Similarly, all devices
in
or V
Table 29, page
CCO
CCINT
XCN05009
ramp rate limits,
supply drops
57. The
).
Digi-
CCO
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