XC3S400-4FT256C Xilinx Inc, XC3S400-4FT256C Datasheet - Page 38

• Manufacturer Part Number: XC3S400-4FT256C
• Description: SEMI CONDUCTOR
• Manufacturer: Xilinx Inc

Specifications of XC3S400-4FT256C

• Case: BGA
• Dc: 04+

Spartan-3 FPGA Family: Functional Description
DFS Clock Output Connections
There are two basic cases that determine how to connect
the DFS clock outputs: on-chip and off-chip, which are illus-
trated in
similar to what has already been described for the DLL
component. See the
Connections, page 34
In the on-chip case, it is possible to connect either of the
DFS’s two output clock signals through general routing
resources to the FPGA’s internal registers. Either a Global
Clock Buffer (BUFG) or a BUFGMUX affords access to the
global clock network. The optional feedback loop is formed
in this way, routing CLK0 to a global clock net, which in turn
drives the CLKFB input.
In the off-chip case, the DFS’s two output clock signals, plus
CLK0 for an optional feedback loop, can exit the FPGA
using output buffers (OBUF) to drive a clock network plus
registers on the board. The feedback loop is formed by
feeding the CLK0 signal back into the FPGA using an
IBUFG, which directly accesses the global clock network, or
an IBUF. Then, the global clock net is connected directly to
the CLKFB input.
Phase Shifter (PS)
The DCM provides two approaches to controlling the phase
of a DCM clock output signal relative to the CLKIN signal:
First, there are nine clock outputs that employ the DLL to
achieve a desired phase relationship: CLK0, CLK90,
CLK180, CLK270, CLK2X, CLK2X180, CLKDV CLKFX,
and CLKFX180. These outputs afford “coarse” phase con-
trol.
The second approach uses the PS component described in
this section to provide a still finer degree of control. The PS
component is only available when the DLL is operating in its
low-frequency mode. The PS component phase shifts the
DCM output clocks by introducing a "fine phase shift" (T
between the CLKFB and CLKIN signals inside the DLL
component. The user can control this fine phase shift down
to a resolution of 1/256 of a CLKIN cycle or one tap delay
(DCM_TAP), whichever is greater. When in use, the PS
component shifts the phase of all nine DCM clock output
signals together. If the PS component is used together with
a DCM clock output such as the CLK90, CLK180, CLK270,
38
54
Figure 19a
and
DLL Clock Output and Feedback
section.
Figure
19c, respectively. This is
www.xilinx.com
PS
)
CLK2X180 and CLKFX180, then the fine phase shift of the
former gets added to the coarse phase shift of the latter.
PS Component Enabling and Mode Selection
The CLKOUT_PHASE_SHIFT attribute enables the PS
component for use in addition to selecting between two
operating modes. As described in
has three possible values: NONE, FIXED and VARIABLE.
When CLKOUT_PHASE_SHIFT is set to NONE, the PS
component is disabled and its inputs, PSEN, PSCLK, and
PSINCDEC, must be tied to GND. The set of waveforms in
Figure 21a
tains a zero-phase alignment of signals CLKFB and CLKIN
upon which the PS component has no effect. The PS com-
ponent is enabled by setting the attribute to either the
FIXED or VARIABLE values, which select the Fixed Phase
mode and the Variable Phase mode, respectively. These
two modes are described in the sections that follow
Determining the Fine Phase Shift
The user controls the phase shift of CLKFB relative to
CLKIN by setting and/or adjusting the value of the
PHASE_SHIFT attribute. This value must be an integer
ranging from –255 to +255. The PS component uses this
value to calculate the desired fine phase shift (T
fraction of the CLKIN period (T
PHASE-SHIFT and T
follows:
Both the Fixed Phase and Variable Phase operating modes
employ this calculation. If the PHASE_SHIFT value is zero,
then CLKFB and CLKIN will be in phase, the same as when
the PS component is disabled. When the PHASE_SHIFT
value is positive, the CLKFB signal will be shifted later in
time with respect to CLKIN. If the attribute value is negative,
the CLKFB signal will be shifted earlier in time with respect
to CLKIN.
The Fixed Phase Mode
This mode fixes the desired fine phase shift to a fraction of
the T
user-selected PHASE_SHIFT value P. The set of wave-
forms in
CLKFB and CLKIN in the Fixed Phase mode. In the Fixed
Phase mode, the PSEN, PSCLK and PSINCDEC inputs are
not used and must be tied to GND.
CLKIN
T
PS
Figure 21b
shows the disabled case, where the DLL main-
, as determined by Equation (4) and its
= (PHASE_SHIFT/256)*T
CLKIN
illustrates the relationship between
, it is possible to calculate T
DS099-2 (v2.2) May 25, 2007
CLKIN
Table
Product Specification
CLKIN
). Given values for
19, this attribute
PS
) as a
PS
(4)
as
R