XC3S400-4FT256C Xilinx Inc, XC3S400-4FT256C Datasheet - Page 85

• Manufacturer Part Number: XC3S400-4FT256C
• Description: SEMI CONDUCTOR
• Manufacturer: Xilinx Inc

Specifications of XC3S400-4FT256C

• Case: BGA
• Dc: 04+

Table 55: Block RAM Timing
Clock Distribution Switching Characteristics
Table 56: Clock Distribution Switching Characteristics
DS099-3 (v2.2) May 25, 2007
Product Specification
98
Notes:
1.
Clock-to-Output Times
T
Setup Times
T
Hold Times
T
Clock Timing
T
T
Global clock buffer (BUFG, BUFGMUX, BUFGCE) I-input to
O-output delay
Global clock multiplexer (BUFGMUX) select S-input setup to
I0- and I1-inputs. Same as BUFGCE enable CE-input
BCKO
BDCK
BCKD
BPWH
BPWL
The numbers in this table are based on the operating conditions set forth in
Symbol
R
When reading from the Block
RAM, the time from the active
transition at the CLK input to
data appearing at the DOUT
output
Time from the setup of data at
the DIN inputs to the active
transition at the CLK input of the
Block RAM
Time from the active transition
at the Block RAM’s CLK input to
the point where data is last held
at the DIN inputs
Block RAM CLK signal High
pulse width
Block RAM CLK signal Low
pulse width
Description
Description
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0.79
0.43
1.19
1.19
Min
Spartan-3 FPGA Family: DC and Switching Characteristics
0
Symbol
T
T
-5
GIO
GSI
Max
2.09
Table
∞
∞
-
-
Speed Grade
Minimum
31.
-MIN
0.14
0.20
0.79
0.49
1.37
1.37
Speed Grade
Min
0
0.36
0.53
-5
-4
Maximum
Max
2.40
∞
∞
-
-
0.41
0.60
-4
Units
ns
ns
ns
ns
ns
Units
ns
ns
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