XC3S400-4FT256C Xilinx Inc, XC3S400-4FT256C Datasheet - Page 16

• Manufacturer Part Number: XC3S400-4FT256C
• Description: SEMI CONDUCTOR
• Manufacturer: Xilinx Inc

Specifications of XC3S400-4FT256C

• Case: BGA
• Dc: 04+

Spartan-3 FPGA Family: Functional Description
Together with placing the appropriate I/O symbol, two exter-
nally applied voltage levels, V
desired signal standard. The V
the output driver. The voltage on these lines determines the
output voltage swing for all standards except GTL and
GTLP.
All single-ended standards except the LVCMOS, LVTTL,
and PCI varieties require a Reference Voltage (V
bias the input-switching threshold. Once a configuration
data file is loaded into the FPGA that calls for the I/Os of a
given bank to use such a signal standard, a few specifically
reserved I/O pins on the same bank automatically convert
to V
these pins remain I/Os because the V
the input-switching threshold, so there is no need for V
Select the V
gle-ended standard according to
Table 7: Single-Ended I/O Standards (Values in Volts)
Differential standards employ a pair of signals, one the
opposite polarity of the other. The noise canceling (e.g.,
Common-Mode Rejection) properties of these standards
permit exceptionally high data transfer rates. This section
16
54
Notes:
1.
2.
3.
GTL
GTLP
HSTL_I
HSTL_III
HSTL_I_18
HSTL_II_18
HSTL_III_18
LVCMOS12
LVCMOS15
LVCMOS18
LVCMOS25
LVCMOS33
LVTTL
PCI33_3
SSTL18_I
SSTL18_II
SSTL2_I
SSTL2_II
(IOSTANDARD)
Standard
REF
Banks 4 and 5 of any Spartan-3 device in a VQ100 package
do not support signal standards using V
The V
be no lower than the termination voltage (V
lower than the voltage at the I/O pad.
See
Signal
inputs. When using one of the LVCMOS standards,
Table 9
CCO
CCO
level used for the GTL and GTLP standards must
for a listing of the single-ended DCI standards.
Outputs
and V
Note 2
Note 2
For
1.5
1.5
1.8
1.8
1.8
1.2
1.5
1.8
2.5
3.3
3.3
3.0
1.8
1.8
2.5
2.5
V
REF
CCO
Inputs
Note 2
Note 2
levels to suit the desired sin-
For
1.2
1.5
1.8
2.5
3.3
3.3
3.0
-
-
-
-
-
-
-
-
-
CCO
CCO
Table
lines provide current to
Inputs
V
and V
REF
0.75
1.25
1.25
0.8
0.9
0.9
0.9
1.1
0.9
0.9
7.
CCO
1
-
-
-
-
-
-
-
REF
for
(1)
.
TT
REF
voltage biases
), nor can it be
Termination
select the
Voltage
Board
(V
0.75
1.25
1.25
1.2
1.5
1.5
0.9
0.9
1.8
0.9
0.9
REF
-
-
-
-
-
-
-
TT
www.xilinx.com
)
REF
) to
.
introduces the differential signaling capabilities of Spartan-3
devices.
Each device-package combination designates specific I/O
pairs that are specially optimized to support differential
standards. A unique “L-number”, part of the pin name, iden-
tifies the line-pairs associated with each bank (see
Figure 38, page
designate the true and inverted lines, respectively. For
example, the pin names IO_L43P_7 and IO_L43N_7 indi-
cate the true and inverted lines comprising the line pair L43
on Bank 7. The V
The V
making them independent of the V
bank. The V
suit the desired differential standard according to
Table 8: Differential I/O Standards
The need to supply V
which standards can be used in the same bank. See
Organization of IOBs into Banks
guidelines concerning the use of the V
Digitally Controlled Impedance (DCI)
When the round-trip delay of an output signal — i.e., from
output to input and back again — exceeds rise and fall
times, it is common practice to add termination resistors to
the line carrying the signal. These resistors effectively
match the impedance of a device’s I/O to the characteristic
impedance of the transmission line, thereby preventing
reflections that adversely affect signal integrity. However,
with the high I/O counts supported by modern devices, add-
ing resistors requires significantly more components and
board area. Furthermore, for some packages — e.g., ball
grid arrays — it may not always be possible to place resis-
tors close to pins.
DCI answers these concerns by providing two kinds of
on-chip terminations: Parallel terminations make use of an
integrated resistor network. Series terminations result from
controlling the impedance of output drivers. DCI actively
adjusts both parallel and series terminations to accurately
Notes:
1.
LDT_25 (ULVDS_25)
LVDS_25
BLVDS_25
LVDSEXT_25
LVPECL_25
RSDS_25
DIFF_HSTL_II_18
DIFF_SSTL2_II
Signal Standard
See
(IOSTANDARD)
CCAUX
Table 9
REF
lines supply power to the differential inputs,
for a listing of the differential DCI standards.
lines are not used. Select the V
105). For each pair, the letters ‘P’ and ‘N’
CCO
REF
lines provide current to the outputs.
Outputs
and V
For
2.5
2.5
2.5
2.5
2.5
2.5
1.8
2.5
V
CCO
CCO
DS099-2 (v2.2) May 25, 2007
(Volts)
CCO
imposes constraints on
section for additional
Inputs
Product Specification
CCO
For
-
-
-
-
-
-
-
-
voltage for an I/O
and V
CCO
V
REF
Table
Inputs
(Volts)
REF
level to
-
-
-
-
-
-
-
-
lines.
for
The
8.
R