XC3S400-4FT256C Xilinx Inc, XC3S400-4FT256C Datasheet - Page 35

• Manufacturer Part Number: XC3S400-4FT256C
• Description: SEMI CONDUCTOR
• Manufacturer: Xilinx Inc

Specifications of XC3S400-4FT256C

• Case: BGA
• Dc: 04+

In the on-chip synchronization case
Figure
output clock signals through general routing resources to
the FPGA’s internal registers. Either a Global Clock Buffer
(BUFG) or a BUFGMUX affords access to the global clock
network. As shown in
ated by routing CLK0 (or CLK2X, in
clock net, which in turn drives the CLKFB input.
In the off-chip synchronization case
Figure
output clock signals exit the FPGA using output buffers
(OBUF) to drive an external clock network plus registers on
the board. As shown in
formed by feeding CLK0 (or CLK2X, in
into the FPGA using an IBUFG, which directly accesses the
global clock network, or an IBUF. Then, the global clock net
is connected directly to the CLKFB input.
DLL Frequency Modes
The DLL supports two distinct operating modes, High Fre-
quency and Low Frequency, with each specified over a differ-
ent clock frequency range. The DLL_FREQUENCY_MODE
DS099-2 (v2.2) May 25, 2007
Product Specification
Notes:
1.
19b), it is possible to connect any of the DLL’s seven
19d), CLK0 (or CLK2X) plus any of the DLL’s other
BUFG
In the Low Frequency mode, all seven DLL outputs are available. In the High Frequency mode, only the CLK0, CLK180,
and CLKDV outputs are available.
R
IBUFG
IBUFG
(c) Off-Chip with CLK0 Feedback
(a) On-Chip with CLK0 Feedback
Figure 19: Input Clock, Output Clock, and Feedback Connections for the DLL
CLKIN
CLKFB
CLKIN
CLKFB
DCM
DCM
Figure
FPGA
Figure
CLK2X180
CLK2X180
FPGA
CLK0
CLK0
CLK180
CLK270
CLK180
CLK270
CLKDV
CLKDV
19a, the feedback loop is cre-
CLK2X
CLK2X
CLK90
CLK90
CLK0
CLK0
19c, the feedback loop is
Figure
BUFGMUX
BUFGMUX
OBUF
OBUF
Figure
(Figure 19a
(Figure 19c
19b) to a global
Net Delay
Clock
Net Delay
Clock
19d) back
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and
and
attribute chooses between the two modes. When the
attribute is set to LOW, the Low Frequency mode permits all
seven DLL clock outputs to operate over a low-to-moderate
frequency range. When the attribute is set to HIGH, the High
Frequency mode allows the CLK0, CLK180 and CLKDV out-
puts to operate at the highest possible frequencies. The
remaining DLL clock outputs are not available for use in High
Frequency mode.
Accommodating High Input Frequencies
If the frequency of the CLKIN signal is high such that it
exceeds the maximum permitted, divide it down to an
acceptable value using the CLKIN_DIVIDE_BY_2 attribute.
When this attribute is set to TRUE, the CLKIN frequency is
divided by a factor of two just as it enters the DCM.
Coarse Phase Shift Outputs of the DLL Compo-
nent
In addition to CLK0 for zero-phase alignment to the CLKIN
signal, the DLL also provides the CLK90, CLK180 and
CLK270 outputs for 90°, 180° and 270° phase-shifted sig-
nals, respectively. These signals are described in
BUFG
IBUFG
IBUFG
Spartan-3 FPGA Family: Functional Description
(d) Off-Chip with CLK2X Feedback
(b) On-Chip with CLK2X Feedback
CLKIN
CLKFB
CLKIN
CLKFB
DCM
DCM
FPGA
CLK2X180
CLK2X180
CLK2X
CLK2X
FPGA
CLK180
CLK270
CLK180
CLK270
CLKDV
CLKDV
CLK90
CLK90
CLK2X
CLK0
CLK2X
CLK0
BUFGMUX
BUFGMUX
OBUF
OBUF
Net Delay
Clock
Net Delay
DS099-2_09_082104
Clock
Table
15.
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