XC3S400-4FT256C Xilinx Inc, XC3S400-4FT256C Datasheet - Page 56

• Manufacturer Part Number: XC3S400-4FT256C
• Description: SEMI CONDUCTOR
• Manufacturer: Xilinx Inc

Specifications of XC3S400-4FT256C

• Case: BGA
• Dc: 04+

Spartan-3 FPGA Family: DC and Switching Characteristics
Table 27: Absolute Maximum Ratings (Continued)
Table 28: Supply Voltage Thresholds for Power-On Reset
56
Notes:
1.
2.
3.
4.
Notes:
1.
2.
3.
Symbol
V
T
T
T
STG
ESD
SOL
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress
ratings only; functional operation of the device at these or any other conditions beyond those listed under the Recommended
Operating Conditions is not implied. Exposure to Absolute Maximum Ratings conditions for extended periods of time adversely
affects device reliability.
All User I/O and Dual-Purpose pins (DIN/D0, D1–D7, CS_B, RDWR_B, BUSY/DOUT, and INIT_B) draw power from the V
power rail of the associated bank. Keeping V
diode junctions that exist between each of these pins and the V
used to determine the max limit. Input voltages outside the -0.5V to V
input clamp diode rating is met and no more than 100 pins exceed the range simultaneously. The V
AC components of signals. Simple application solutions are available that show how to handle overshoot/undershoot as well as
achieve PCI compliance. Refer to the following application notes: "Virtex™-II Pro and Spartan-3 3.3V PCI Reference Design"
(XAPP653) and "Using 3.3V I/O Guidelines in a Virtex-II Pro Design" (XAPP659).
All Dedicated pins (M0–M2, CCLK, PROG_B, DONE, HSWAP_EN, TCK, TDI, TDO, and TMS) draw power from the V
(2.5V). Meeting the V
do not turn on.
recommended operating level (2.625V), V
For information concerning the use of 3.3V signals, see the
For soldering guidelines, see "Device Packaging and Thermal Characteristics" (UG112) and "Implementation and Solder Reflow
Guidelines for Pb-Free Packages" (XAPP427).
V
may draw a surplus current in addition to the quiescent current levels specified in
current. The FPGA does not use any of the surplus current for the power-on process. For this power sequence, make sure that
regulators with foldback features will not shut down inadvertently.
To ensure successful power-on, V
ranges with no dips at any point.
If a brown-out condition occurs where V
V
J
CCINT
CCINT
V
Symbol
V
V
CCAUXT
CCINTT
CCO4T
, V
must drop below the minimum power-on reset voltage in order to clear out the device configuration content.
Electrostatic Discharge Voltage pins relative
to GND
Junction temperature
Soldering temperature
Storage temperature
CCAUX
Table 31
, and V
Threshold for the V
Threshold for the V
Threshold for the V
IN
CCO
max limit ensures that the internal diode junctions that exist between each of these pins and the V
Description
specifies the V
supplies may be applied in any order. When applying V
CCINT
CCAUX
, V
CCAUX
IN
CCINT
CCAUX
CCO
CCO
max < 3.125V. As long as the V
Description
IN
range used to determine the max limit. When V
Bank 4, and V
or V
Bank 4 supply
within 500 mV of the associated V
supply
supply
CCINT
Human body model
Charged device model
Machine model
www.xilinx.com
drops below the retention voltage indicated in
3.3V-Tolerant Configuration Interface, page
CCAUX
CCO
and GND rails do not turn on.
Conditions
supplies must rise through their respective threshold-voltage
CCO
+0.5V voltage range are permissible provided that the I
IN
max specification is met, oxide stress is not possible.
Table
CCO
CCINT
rails or ground rail ensures that the internal
33. Applying V
Min
power before V
0.4
0.8
0.4
CCAUX
Table 31
Min
–65
IN
-
-
-
-
limits apply to both the DC and
is at its maximum
CCAUX
DS099-3 (v2.2) May 25, 2007
Table
CCAUX
Max
specifies the V
1.0
2.0
1.0
46.
Product Specification
eliminates the surplus
30, then V
±2000
±500
±200
Max
125
220
150
power, the FPGA
CCAUX
CCO
CCAUX
CCAUX
Units
CCO
V
V
V
Units
range
°C
°C
°C
rail
V
V
V
or
rail
IK
R