XC3S400-4FT256C Xilinx Inc, XC3S400-4FT256C Datasheet - Page 95

• Manufacturer Part Number: XC3S400-4FT256C
• Description: SEMI CONDUCTOR
• Manufacturer: Xilinx Inc

Specifications of XC3S400-4FT256C

• Case: BGA
• Dc: 04+

Table 66: Timing for the Master and Slave Parallel Configuration Modes (Continued)
DS099-3 (v2.2) May 25, 2007
Product Specification
98
Notes:
1.
2.
3.
4.
Hold Times
T
T
T
Clock Timing
T
T
F
ΔF
SMCCD
SMCCCS
SMWCC
CCH
CCL
CCPAR
Symbol
CCPAR
The numbers in this table are based on the operating conditions set forth in
RDWR_B is synchronized to CCLK for the purpose of performing the Abort operation. The same pin asynchronously controls the
driver impedance of the D0 - D7 pins. To avoid contention when writing configuration data to the D0 - D7 bus, do not bring RDWR_B
High when CS_B is Low.
In the Slave Parallel mode, it is necessary to use the BUSY pin when the CCLK frequency exceeds this maximum specification.
Some Xilinx documents may refer to Parallel modes as "SelectMAP" modes.
(2)
R
The time from the rising transition at the CCLK pin to the point
when data is last held at the D0-D7 pins
The time from the rising transition at the CCLK pin to the point
when a logic level is last held at the CS_B pin
The time from the rising transition at the CCLK pin to the point
when a logic level is last held at the RDWR_B pin
CCLK input pin High pulse width
CCLK input pin Low pulse width
Frequency of the
clock signal at the
CCLK input pin
Variation from the CCLK output frequency set using the BitGen
option ConfigRate
No bitstream
compression
With bitstream compression
During STARTUP phase
Description
www.xilinx.com
Not using the BUSY pin
Using the BUSY pin
Spartan-3 FPGA Family: DC and Switching Characteristics
Table
31.
(3)
Master
Master
Slave/
Slave
Both
All Speed Grades
–50%
Min
0
0
0
5
5
0
0
0
0
+50%
Max
50
66
20
50
∞
∞
-
-
-
Units
MHz
MHz
MHz
MHz
ns
ns
ns
ns
ns
-
95