XC3S400-4FT256C Xilinx Inc, XC3S400-4FT256C Datasheet - Page 12

• Manufacturer Part Number: XC3S400-4FT256C
• Description: SEMI CONDUCTOR
• Manufacturer: Xilinx Inc

Specifications of XC3S400-4FT256C

• Case: BGA
• Dc: 04+

Spartan-3 FPGA Family: Functional Description
IOBs
For additional information, refer to the “Using I/O
Resources” chapter in UG331.
IOB Overview
The Input/Output Block (IOB) provides a programmable,
bidirectional interface between an I/O pin and the FPGA’s
internal logic.
A simplified diagram of the IOB’s internal structure appears
in
IOB: the output path, input path, and 3-state path. Each
path has its own pair of storage elements that can act as
either registers or latches. For more information, see the
Storage Element Functions
nal paths are as follows:
•
•
•
Table 4: Storage Element Signal Description
12
54
D
Q
CK
CE
SR
REV
Element
Storage
Signal
Figure
The input path carries data from the pad, which is
bonded to a package pin, through an optional
programmable delay element directly to the I line.
There are alternate routes through a pair of storage
elements to the IQ1 and IQ2 lines. The IOB outputs I,
IQ1, and IQ2 all lead to the FPGA’s internal logic. The
delay element can be set to ensure a hold time of zero.
The output path, starting with the O1 and O2 lines,
carries data from the FPGA’s internal logic through a
multiplexer and then a three-state driver to the IOB
pad. In addition to this direct path, the multiplexer
provides the option to insert a pair of storage elements.
The 3-state path determines when the output driver is
high impedance. The T1 and T2 lines carry data from
the FPGA’s internal logic through a multiplexer to the
5. There are three main signal paths within the
Data input
Data output
Clock input
Clock Enable input
Set/Reset
Reverse
Description
section. The three main sig-
Data at this input is stored on the active edge of CK enabled by CE. For latch operation when the
input is enabled, data passes directly to the output Q.
The data on this output reflects the state of the storage element. For operation as a latch in
transparent mode, Q will mirror the data at D.
A signal’s active edge on this input with CE asserted, loads data into the storage element.
When asserted, this input enables CK. If not connected, CE defaults to the asserted state.
Forces storage element into the state specified by the SRHIGH/SRLOW attributes. The
SYNC/ASYNC attribute setting determines if the SR input is synchronized to the clock or not.
Used together with SR. Forces storage element into the state opposite from what SR does.
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•
Storage Element Functions
There are three pairs of storage elements in each IOB, one
pair for each of the three paths. It is possible to configure
each of these storage elements as an edge-triggered
D-type flip-flop (FD) or a level-sensitive latch (LD).
The storage-element-pair on either the Output path or the
Three-State path can be used together with a special multi-
plexer to produce Double-Data-Rate (DDR) transmission.
This is accomplished by taking data synchronized to the
clock signal’s rising edge and converting them to bits syn-
chronized on both the rising and the falling edge. The com-
bination of two registers and a multiplexer is referred to as a
Double-Data-Rate D-type flip-flop (FDDR).
See
information.
The signal paths associated with the storage element are
described in
output driver. In addition to this direct path, the
multiplexer provides the option to insert a pair of
storage elements. When the T1 or T2 lines are
asserted High, the output driver is high-impedance
(floating, Hi-Z). The output driver is active-Low
enabled.
All signal paths entering the IOB, including those
associated with the storage elements, have an inverter
option. Any inverter placed on these paths is
automatically absorbed into the IOB.
Double-Data-Rate Transmission, page 14
Function
Table
4.
DS099-2 (v2.2) May 25, 2007
Product Specification
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