XC3S400-4FT256C Xilinx Inc, XC3S400-4FT256C Datasheet - Page 25

• Manufacturer Part Number: XC3S400-4FT256C
• Description: SEMI CONDUCTOR
• Manufacturer: Xilinx Inc

Specifications of XC3S400-4FT256C

• Case: BGA
• Dc: 04+

The aspect ratio — i.e., width vs. depth — of each block
RAM is configurable. Furthermore, multiple blocks can be
cascaded to create still wider and/or deeper memories.
A choice among primitives determines whether the block
RAM functions as dual- or single-port memory. A name of
the form RAMB16_S[w
itive, where the integers w
path width at ports w
RAMB16_S9_S18 is a dual-port RAM with a 9-bit-wide Port
A and an 18-bit-wide Port B. A name of the form
RAMB16_S[w] identifies the single-port primitive, where the
integer w specifies the total data path width of the lone port.
A RAMB16_S18 is a single-port RAM with an 18-bit-wide
port. Other memory functions — e.g., FIFOs, data path
width conversion, ROM, etc. — are readily available using
the CORE Generator™ system, part of the Xilinx develop-
ment software.
Arrangement of RAM Blocks on Die
The XC3S50 has one column of block RAM. The Spartan-3
devices ranging from the XC3S200 to XC3S2000 have two
columns of block RAM. The XC3S4000 and XC3S5000
have four columns. The position of the columns on the die is
shown in
available RAM blocks are distributed equally among the col-
umns.
storage capacity, and the number of columns for each
device.
Table 11: Number of RAM Blocks by Device
DS099-2 (v2.2) May 25, 2007
Product Specification
XC3S50
XC3S200
XC3S400
XC3S1000
XC3S1500
XC3S2000
XC3S4000
XC3S5000
Device
Table 11
Figure 1, page
R
of RAM Blocks
Total Number
shows the number of RAM blocks, the data
104
12
16
24
32
40
96
4
A
]_S[w
A
4. For a given device, the total
and w
A
and w
B
] calls out the dual-port prim-
Locations (bits)
Addressable
B
1,769,472
1,916,928
, respectively. Thus, a
221,184
294,912
442,368
589,824
737,280
73,728
B
Total
specify the total data
Columns
Number
of
1
2
2
2
2
2
4
4
www.xilinx.com
Block RAM and multipliers have interconnects between
them that permit simultaneous operation; however, since
the multiplier shares inputs with the upper data bits of block
RAM, the maximum data path width of the block RAM is 18
bits in this case.
The Internal Structure of the Block RAM
The block RAM has a dual port structure. The two identical
data ports called A and B permit independent access to the
common RAM block, which has a maximum capacity of
18,432 bits — or 16,384 bits when no parity lines are used.
Each port has its own dedicated set of data, control and
clock lines for synchronous read and write operations.
There are four basic data paths, as shown in
write to and read from Port A, (2) write to and read from Port
B, (3) data transfer from Port A to Port B, and (4) data trans-
fer from Port B to Port A.
Block RAM Port Signal Definitions
Representations
RAMB16_S[w
RAMB16_S[w] with their associated signals are shown in
Figure 12a
defined in
4
1
Read
Write
Write
Read
Spartan-3 FPGA Family: Functional Description
Table
and
Figure 11: Block RAM Data Paths
A
]_S[w
Figure
12.
B
of
]
Block RAM
12b, respectively. These signals are
Spartan-3
Dual Port
and
the
the
dual-port
single-port
Figure
DS099-2_12_030703
Write
Read
Read 3
Write
primitive
primitive
11: (1)
2
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