XC3S400-4FT256C Xilinx Inc, XC3S400-4FT256C Datasheet - Page 99

• Manufacturer Part Number: XC3S400-4FT256C
• Description: SEMI CONDUCTOR
• Manufacturer: Xilinx Inc

Specifications of XC3S400-4FT256C

• Case: BGA
• Dc: 04+

DS099-4 (v2.2) May 25, 2007
Introduction
This data sheet module describes the various pins on a
Spartan™-3 FPGA and how they connect to the supported
component packages.
•
•
•
•
Table 68: Types of Pins on Spartan-3 FPGAs
DS099-4 (v2.2) May 25, 2007
Product Specification
CONFIG
DUAL
Type/
Color
Code
JTAG
© 2003-2006 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm.
The
pins by their function type.
The
description for each pin on the device.
The
offers significantly more detail about each pin,
especially for the dual- or special-function pins used
during device configuration.
Some pins have associated behavior that is controlled
by settings in the configuration bitstream. These
options are described in the
section.
DCI
I/O
Pin Types
Detailed, Functional Pin Descriptions
Pin Definitions
All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.
Unrestricted, general-purpose user-I/O pin. Most pins can be paired
together to form differential I/Os.
Dual-purpose pin used in some configuration modes during the
configuration process and then usually available as a user I/O after
configuration. If the pin is not used during configuration, this pin behaves
as an I/O-type pin. There are 12 dual-purpose configuration pins on every
package. The INIT_B pin has an internal pull-up resistor to VCCO_4 or
VCCO_BOTTOM during configuration.
Dedicated configuration pin. Not available as a user-I/O pin. Every
package has seven dedicated configuration pins. These pins are powered
by VCCAUX and have a dedicated internal pull-up resistor to VCCAUX
during configuration.
Dedicated JTAG pin. Not available as a user-I/O pin. Every package has
four dedicated JTAG pins. These pins are powered by VCCAUX and have
a dedicated internal pull-up resistor to VCCAUX during configuration.
Dual-purpose pin that is either a user-I/O pin or used to calibrate output
buffer impedance for a specific bank using Digital Controlled Impedance
(DCI). There are two DCI pins per I/O bank.
section categorizes all of the FPGA
section provides a top-level
R
Bitstream Options
Description
section
208
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0
Spartan-3 FPGA Family:
Pinout Descriptions
Product Specification
•
Pin Descriptions
Pin Types
A majority of the pins on a Spartan-3 FPGA are gen-
eral-purpose, user-defined I/O pins. There are, however, up
to 12 different functional types of pins on Spartan-3 pack-
ages, as outlined in
ings that follow, the individual pins are color-coded
according to pin type as in the table.
The
packaging options available for Spartan-3 FPGAs.
Detailed pin list tables and footprint diagrams are
provided for each package solution.
Package Overview
Table
68. In the package footprint draw-
IO,
IO_Lxxy_#
IO_Lxxy_#/DIN/D0,
IO_Lxxy_#/D1, IO_Lxxy_#/D2,
IO_Lxxy_#/D3, IO_Lxxy_#/D4,
IO_Lxxy_#/D5, IO_Lxxy_#/D6,
IO_Lxxy_#/D7,
IO_Lxxy_#/CS_B,
IO_Lxxy_#/RDWR_B,
IO_Lxxy_#/BUSY/DOUT,
IO_Lxxy_#/INIT_B
CCLK, DONE, M2, M1, M0,
PROG_B, HSWAP_EN
TDI, TMS, TCK, TDO
IO/VRN_#
IO_Lxxy_#/VRN_#
IO/VRP_#
IO_Lxxy_#/VRP_#
section describes the various
Pin Name(s) in Type
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