XC3S400-4FT256C Xilinx Inc, XC3S400-4FT256C Datasheet - Page 20

• Manufacturer Part Number: XC3S400-4FT256C
• Description: SEMI CONDUCTOR
• Manufacturer: Xilinx Inc

Specifications of XC3S400-4FT256C

• Case: BGA
• Dc: 04+

Spartan-3 FPGA Family: Functional Description
The DCI feature operates independently for each of the
device’s eight banks. Each bank has an ‘N’ reference pin
(VRN) and a ‘P’ reference pin, (VRP), to calibrate driver and
termination resistance. Only when using a DCI standard on
a given bank do these two pins function as VRN and VRP.
When not using a DCI standard, the two pins function as
user I/Os. As shown in
resistor to pull the VRN pin up to V
ence resistor to pull the VRP pin down to GND. Also see
Figure 40, page
commonly 50 Ohms — with one-percent tolerance, which is
either the characteristic impedance of the line or twice that,
depending on the DCI standard in use. Standards having a
symbol name that contains the letters “DV2” use a refer-
ence resistor value that is twice the line impedance. DCI
adjusts the output driver impedance to match the reference
resistors’ value or half that, according to the standard. DCI
always adjusts the on-chip termination resistors to directly
match the reference resistors’ value.
The rules guiding the use of DCI standards on banks are as
follows:
1. No more than one DCI I/O standard with a Single
2. No more than one DCI I/O standard with a Split
3. Single Termination, Split Termination, Controlled-
See also
ately below, and
Impedance Resistor Reference Input, page
The Organization of IOBs into Banks
IOBs are allocated among eight banks, so that each side of
the device has two banks, as shown in
packages, each bank has independent V
example, V
lines going to all other banks.
For the Very Thin Quad Flat Pack (VQ), Plastic Quad Flat
Pack (PQ), Fine Pitch Thin Ball Grid Array (FT), and Fine
Pitch Ball Grid Array (FG) packages, each bank has dedi-
20
54
Figure 7: Connection of Reference Resistors (R
Termination is allowed per bank.
Termination is allowed per bank.
Impedance Driver, and Controlled-Impedance Driver
with Half Impedance can co-exist in the same bank.
The Organization of IOBs into
REF
One of eight
I/O Banks
Bank 3 lines are separate from the V
109. Both resistors have the same value —
DCI: User I/O or Digitally Controlled
VRN
VRP
Figure
7, add an external reference
V CCO
DS099-2_04_082104
CCO
R
R
REF
REF
and another refer-
(1%)
(1%)
Figure
Banks, immedi-
REF
109.
lines. For
8. For all
REF
www.xilinx.com
REF
)
cated V
separate from the V
Spartan-3 devices in these packages support eight inde-
pendent V
In contrast, the 144-pin Thin Quad Flat Pack (TQ144) pack-
age and the 132-pin Chip-Scale Package (CP132) tie V
together internally for the pair of banks on each side of the
device. For example, the V
lines are tied together. The interconnected bank-pairs are
0/1, 2/3, 4/5, and 6/7. As a result, Spartan-3 devices in the
CP132 and TQ144 packages support four independent
V
Spartan-3 Compatibility
Within the Spartan-3 family, all devices are pin-compatible
by package. When the need for future logic resources out-
grows the capacity of the Spartan-3 device in current use, a
larger device in the same package can serve as a direct
replacement. Larger devices may add extra V
lines to support a greater number of I/Os. In the larger
device, more pins can convert from user I/Os to V
Also, additional V
“not connected” in the smaller device. Thus, it is important
to plan for future upgrades at the time of the board’s initial
design by laying out connections to the extra pins.
The Spartan-3 family is not pin-compatible with any previ-
ous Xilinx FPGA family or with other platforms among the
Spartan-3 Generation FPGAs.
Rules Concerning Banks
When assigning I/Os to banks, it is important to follow the
following V
1. Leave no V
2. Set all V
3. The V
CCO
bank to the same voltage level.
I/Os of the (interconnected) bank(s) must agree. The
supplies.
CCO
Figure 8: Spartan-3 I/O Banks (top view)
CCO
CCO
CCO
lines. For example, the V
CCO
supplies.
levels used by all standards assigned to the
rules:
CCO
lines associated with the (interconnected)
CCO
CCO
pins unconnected on the FPGA.
Bank 0
Bank 5
lines are bonded out to pins that were
lines going to all other banks. Thus,
CCO
Bank 0 and the V
Bank 1
Bank 4
DS099-2 (v2.2) May 25, 2007
DS099-2_03_082104
CCO
Product Specification
Bank 7 lines are
REF
CCO
and V
REF
Bank 1
lines.
CCO
CCO
R