XC3S400-4FT256C Xilinx Inc, XC3S400-4FT256C Datasheet - Page 55

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XC3S400-4FT256C

Manufacturer Part Number
XC3S400-4FT256C
Description
SEMI CONDUCTOR
Manufacturer
Xilinx Inc
Datasheet

Specifications of XC3S400-4FT256C

Case
BGA
Dc
04+

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DS099-3 (v2.2) May 25, 2007
DC Electrical Characteristics
In this section, specifications may be designated as
Advance, Preliminary, or Production. These terms are
defined as follows:
Advance: Initial estimates are based on simulation, early
characterization, and/or extrapolation from the characteris-
tics of other families. Values are subject to change.
Although speed grades with this designation are considered
relatively stable and conservative, some under-reporting
might still occur. Use as estimates, not for production.
Preliminary: Based on complete early silicon characteriza-
tion. Devices and speed grades with this designation are
intended to give a better indication of the expected perfor-
mance
under-reported delays is greatly reduced compared to
Advance data. Use as estimates, not for production.
Production: These specifications are approved only after
silicon has been characterized over numerous production
lots. There is no under-reporting of delays, and customers
receive formal notification of any subsequent changes.
Parameter values are considered stable with no future
changes expected.
Production-quality systems must only use FPGA designs
compiled with a Production status speed file. FPGA designs
using a less mature speed file designation should only be
used during system prototyping or preproduction qualifica-
tion. FPGA designs with speed files designated as Preview,
Advance, or Preliminary should not be used in a produc-
tion-quality system.
Table 27: Absolute Maximum Ratings
DS099-3 (v2.2) May 25, 2007
Product Specification
Symbol
V
V
V
V
CCAUX
CCINT
© 2003-2007 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm.
V
CCO
REF
I
IK
IN
of
All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.
Internal supply voltage relative to GND
Auxiliary supply voltage relative to GND
Output driver supply voltage relative to GND
Input reference voltage relative to GND
Voltage applied to all User I/O pins and
Dual-Purpose pins relative to GND
Voltage applied to all Dedicated pins
relative to GND
Input clamp current per I/O pin
production
Description
(3)
silicon.
R
The
(2)
probability
98
Driver in a
high-impedance
state
–0.5 V
www.xilinx.com
of
0
< V
Spartan-3 FPGA Family:
DC and Switching Characteristics
Product Specification
Whenever a speed file designation changes, as a device
matures toward Production status, rerun the
ISE
FPGA design incorporates the latest timing information and
software updates.
All parameter limits are representative of worst-case supply
voltage and junction temperature conditions. The following
applies unless otherwise noted: The parameter values
published in this module apply to all Spartan™-3
devices. AC and DC characteristics are specified using
the same numbers for both commercial and industrial
grades. All parameters representing voltages are mea-
sured with respect to GND.
Some specifications list different values for one or more die
or mask revisions, indicated by the device top marking.
If a particular Spartan-3 FPGA differs in functional behavior
or electrical characteristic from this data sheet, those differ-
ences are described in a separate errata document. The
errata notices for Spartan-3 FPGAs are living documents
and are available online. Also, create a Xilinx MySupport
user account and sign up for automatic E-mail notification
whenever this data sheet or an errata notice is updated.
IN
Conditions
< (V
TM
Spartan-3 Errata Notices
www.xilinx.com/xlnx/xweb/xil_publications_display.jsp?
category=-1210888
To Sign Up for Alerts on Xilinx MySupport
http://www.xilinx.com/xlnx/xil_ans_display.jsp?
getPagePath=19380
software
CCO
Commercial
Industrial
All temp. ranges
+ 0.5 V)
on the FPGA design to ensure that the
–0.95
–0.85
–0.5
–0.5
–0.5
–0.5
–0.5
Min
-
V
V
CCAUX
CCO
±100
Max
1.32
3.00
3.75
4.4
4.3
+ 0.5
+ 0.5
latest Xilinx
Units
mA
V
V
V
V
V
V
55

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