XC3S400-4FT256C Xilinx Inc, XC3S400-4FT256C Datasheet - Page 93

• Manufacturer Part Number: XC3S400-4FT256C
• Description: SEMI CONDUCTOR
• Manufacturer: Xilinx Inc

Specifications of XC3S400-4FT256C

• Case: BGA
• Dc: 04+

Table 65: Timing for the Master and Slave Serial Configuration Modes
DS099-3 (v2.2) May 25, 2007
Product Specification
98
CCLK
DIN
DOUT
INIT_B
Notes:
1.
2.
PROG_B
Clock-to-Output Times
T
Setup Times
T
Hold Times
T
Clock Timing
T
T
F
ΔF
(Input)
(Open-Drain)
(Input/Output)
(Input)
(Output)
Symbol
CCO
DCC
CCD
CCH
CCL
CCSER
CCSER
The numbers in this table are based on the operating conditions set forth in
For serial configuration with a daisy-chain of multiple FPGAs, the maximum limit is 25 MHz.
R
The time from the falling transition on the CCLK pin to data
appearing at the DOUT pin
The time from the setup of data at the DIN pin to the rising transition
at the CCLK pin
The time from the rising transition at the CCLK pin to the point when
data is last held at the DIN pin
CCLK input pin High pulse width
CCLK input pin Low pulse width
Frequency of the clock signal at
the CCLK input pin
Variation from the CCLK output frequency set using the ConfigRate
BitGen option
Figure 35: Waveforms for Master and Slave Serial Configuration
Description
T
DCC
Bit 0
No bitstream compression
With bitstream compression
During STARTUP phase
www.xilinx.com
T
CCD
Bit 1
Spartan-3 FPGA Family: DC and Switching Characteristics
Table
31.
Master
Master
Slave/
Slave
T
Both
Both
Both
CCL
Bit n
1/F
CCSER
T
CCO
All Speed Grades
Bit n-64
Bit n+1
–50%
10.0
Min
1.5
5.0
5.0
0
0
0
0
T
CCH
Bit n-63
+50%
66
Max
12.0
20
50
∞
∞
-
-
(2)
DS099-3_04_071604
Units
MHz
MHz
MHz
ns
ns
ns
ns
ns
-
93