XC3S400-4FT256C Xilinx Inc, XC3S400-4FT256C Datasheet - Page 41

• Manufacturer Part Number: XC3S400-4FT256C
• Description: SEMI CONDUCTOR
• Manufacturer: Xilinx Inc

Specifications of XC3S400-4FT256C

• Case: BGA
• Dc: 04+

Table 22: DCM STATUS Bus
Table 23: Status Attributes
Stabilizing DCM Clocks Before User Mode
It is possible to delay the completion of device configuration
until after the DLL has achieved a lock condition using the
STARTUP_WAIT attribute described in
option ensures that the FPGA does not enter user mode —
i.e., begin functional operation — until all system clocks
generated by the DCM are stable. In order to achieve the
delay, it is necessary to set the attribute to TRUE as well as
set the BitGen option LCK_cycle to one of the six cycles
making up the Startup phase of configuration. The selected
cycle defines the point at which configuration will halt until
the LOCKED output goes High.
Global Clock Network
Spartan-3 devices have eight Global Clock inputs called
GCLK0 - GCLK7. These inputs provide access to a
low-capacitance, low-skew network that is well-suited to
carrying high-frequency signals. The Spartan-3 clock net-
work is shown in
located in the center of the bottom edge. GCLK4 through
GCLK7 are located in the center of the top edge.
Eight Global Clock Multiplexers (also called BUFGMUX ele-
ments) are provided that accept signals from Global Clock
inputs and route them to the internal clock network as well
as DCMs. Four BUFGMUX elements are located in the cen-
ter of the bottom edge, just above the GCLK0 - GCLK3
inputs. The remaining four BUFGMUX elements are located
DS099-2 (v2.2) May 25, 2007
Product Specification
Notes:
1.
2.
STARTUP_WAIT
Bit
3:7
0
1
2
The DLL phase shift with all delay taps active is specified as the parameter FINE_SHIFT_RANGE.
If only the DFS clock outputs are used, but none of the DLL clock outputs, this bit will not go High when the CLKIN signal stops.
Attribute
Phase Shift
Overflow
CLKIN Input
Stopped Toggling
CLKFX/CLKFX180
Output Stopped
Toggling
Reserved
R
Name
Figure
Delays transition from configuration to user mode until lock condition is achieved. TRUE, FALSE
22. GCLK0 through GCLK3 are
A value of 1 indicates a phase shift overflow when one of two conditions occurs:
•
•
A value of 1 indicates that the CLKIN input signal is not toggling. A value of 0 indicates
toggling. This bit functions only when the CLKFB input is connected.
A value of 1 indicates that the CLKFX or CLKFX180 output signals are not toggling. A
value of 0 indicates toggling. This bit functions only when using the Digital Frequency
Synthesizer (DFS).
-
Incrementing (or decrementing) TPS beyond 255/256 of a CLKIN cycle.
The DLL is producing its maximum possible phase shift (i.e., all delay taps are
active).
(1)
Table
23. This
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Description
in the center of the top edge, just below the GCLK4 -
GCLK7 inputs.
Pairs of BUFGMUX elements share global inputs, as shown
in
both potentially connect to BUFGMUX4 and BUFGMUX5
located in the upper right center. A differential clock input
uses a pair of GCLK inputs to connect to a single BUFG-
MUX element.
Each BUFGMUX element, shown in
multiplexer that can receive signals from any of the four fol-
lowing sources:
1. One of the four Global Clock inputs on the same side of
2. Any of four nearby horizontal Double lines.
3. Any of four outputs from the DCM in the right-hand
4. Any of four outputs from the DCM in the left-hand
The multiplexer select line, S, chooses which of the two
inputs, I0 or I1, drives the BUFGMUX’s output signal, O, as
described in
other is glitchless, and done in such a way that the output
High and Low times are never shorter than the shortest
High or Low time of either input clock.
Figure
the die — top or bottom — as the BUFGMUX element in
use.
quadrant that is on the same side of the die as the
BUFGMUX element in use.
quadrant that is on the same side of the die as the
BUFGMUX element in use.
Description
Spartan-3 FPGA Family: Functional Description
22. For example, the GCLK4 and GCLK5 inputs
Table
24. The switching from one clock to the
(2)
Figure
22, is a 2-to-1
Values
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