XC3S400-4FT256C Xilinx Inc, XC3S400-4FT256C Datasheet - Page 5

• Manufacturer Part Number: XC3S400-4FT256C
• Description: SEMI CONDUCTOR
• Manufacturer: Xilinx Inc

Specifications of XC3S400-4FT256C

• Case: BGA
• Dc: 04+

Configuration
Spartan-3 FPGAs are programmed by loading configuration
data into robust, reprogrammable, static CMOS configura-
tion latches (CCLs) that collectively control all functional
elements and routing resources. Before powering on the
FPGA, configuration data is stored externally in a PROM or
some other nonvolatile medium either on or off the board.
After applying power, the configuration data is written to the
FPGA using any of five different modes: Master Parallel,
Slave Parallel, Master Serial, Slave Serial, and Boundary
Scan (JTAG). The Master and Slave Parallel modes use an
8-bit wide SelectMAP™ port.
Table 2: Signal Standards Supported by the Spartan-3 Family
DS099-1 (v2.2) May 25, 2007
Product Specification
Single-Ended
GTL
HSTL
LVCMOS
LVTTL
PCI
SSTL
Differential
LDT
(ULVDS)
LVDS
LVPECL
RSDS
HSTL
SSTL
Standard
Category
R
Gunning Transceiver Logic
High-Speed Transceiver Logic
Low-Voltage CMOS
Low-Voltage Transistor-Transistor Logic
Peripheral Component Interconnect
Stub Series Terminated Logic
Lightning Data Transport (HyperTransport™)
Logic
Low-Voltage Differential Signaling
Low-Voltage Positive Emitter-Coupled Logic
Reduced-Swing Differential Signaling
Differential High-Speed Transceiver Logic
Differential Stub Series Terminated Logic
Description
www.xilinx.com
Spartan-3 FPGA Family: Introduction and Ordering Information
V
N/A
(V)
1.5
1.8
1.2
1.5
1.8
2.5
3.3
3.3
3.0
1.8
2.5
2.5
2.5
2.5
1.8
2.5
CCO
The recommended memory for storing the configuration
data is the low-cost Xilinx Platform Flash PROM family,
which includes the XCF00S PROMs for serial configuration
and the higher density XCF00P PROMs for parallel or serial
configuration.
I/O Capabilities
The SelectIO feature of Spartan-3 devices supports 18 sin-
gle-ended standards and 8 differential standards as listed in
Table
uses integrated terminations to eliminate unwanted signal
reflections.
as the number of differential I/O pairs available for each
device/package combination.
2. Many standards support the DCI feature, which
Extended Mode
N/A (±13.4 mA)
N/A (±6.7 mA)
Terminated
Table 3
Standard
33 MHz
Class
Plus
N/A
N/A
N/A
N/A
N/A
N/A
N/A
Bus
N/A
N/A
III
III
II
II
II
II
I
I
I
shows the number of user I/Os as well
(IOSTANDARD)
DIFF_HSTL_II_18
DIFF_SSTL2_II
LVDSEXT_25
HSTL_III_18
LVPECL_25
HSTL_II_18
LVCMOS12
LVCMOS15
LVCMOS18
LVCMOS25
LVCMOS33
HSTL_I_18
BLVDS_25
SSTL18_II
SSTL18_I
RSDS_25
LVDS_25
SSTL2_II
Symbol
HSTL_III
PCI33_3
SSTL2_I
LDT_25
HSTL_I
LVTTL
GTLP
GTL
Option
DCI
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
No
No
No
No
No
No
No
No
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