XC3S400-4FT256C Xilinx Inc, XC3S400-4FT256C Datasheet - Page 109

• Manufacturer Part Number: XC3S400-4FT256C
• Description: SEMI CONDUCTOR
• Manufacturer: Xilinx Inc

Specifications of XC3S400-4FT256C

• Case: BGA
• Dc: 04+

DCI: User I/O or Digitally Controlled
Impedance Resistor Reference Input
These pins are individual user-I/O pins unless one of the I/O
standards used in the bank requires the Digitally Controlled
Impedance (DCI) feature. If DCI is used, then 1% precision
resistors connected to the VRP_# and VRN_# pins match
the impedance on the input or output buffers of the I/O stan-
dards that use DCI within the bank.
The ‘#’ character in the pin name indicates the associated
I/O bank and is an integer, 0 through 7.
There are two DCI pins per I/O bank, except in the CP132
and TQ144 packages, which do not have any DCI inputs for
Bank 5.
VRP and VRN Impedance Resistor Reference
Inputs
The 1% precision impedance-matching resistor attached to
the VRP_# pin controls the pull-up impedance of PMOS
transistor in the input or output buffer. Consequently, the
VRP_# pin must connect to ground. The ‘P’ character in
“VRP” indicates that this pin controls the I/O buffer’s PMOS
transistor impedance. The VRP_# pin is used for both single
and split termination.
The 1% precision impedance-matching resistor attached to
the VRN_# pin controls the pull-down impedance of NMOS
transistor in the input or output buffer. Consequently, the
VRN_# pin must connect to VCCO. The ‘N’ character in
“VRN” indicates that this pin controls the I/O buffer’s NMOS
transistor impedance. The VRN_# pin is only used for split
termination.
Each VRN or VRP reference input requires its own resistor.
A single resistor cannot be shared between VRN or VRP
pins associated with different banks.
During configuration, these pins behave exactly like
user-I/O pins. The associated DCI behavior is not active or
valid until after configuration completes.
Also see
DS099-4 (v2.2) May 25, 2007
Product Specification
(a) No termination
Digitally Controlled Impedance (DCI), page
One of eight
I/O Banks
R
User I/O
User I/O
(b) Single termination
Figure 40: DCI Termination Types
One of eight
I/O Banks
www.xilinx.com
16.
VRN
VRP
DCI Termination Types
If the I/O in an I/O bank do not use the DCI feature, then no
external resistors are required and both the VRP_# and
VRN_# pins are available for user I/O, as shown in
Figure
If the I/O standards within the associated I/O bank require
single termination—such as GTL_DCI, GTLP_DCI, or
HSTL_III_DCI—then only the VRP_# signal connects to a
1% precision impedance-matching resistor, as shown in
Figure
Finally, if the I/O standards with the associated I/O bank
require
SSTL2_I_DCI, SSTL2_II_DCI, or LVDS_25_DCI and
LVDSEXT_25_DCI receivers—then both the VRP_# and
VRN_# pins connect to separate 1% precision imped-
ance-matching resistors, as shown in
pin is available for user I/O.
GCLK: Global Clock Buffer Inputs or
General-Purpose I/O Pins
These pins are user-I/O pins unless they specifically con-
nect to one of the eight low-skew global clock buffers on the
device, specified using the IBUFG primitive.
There are eight GCLK pins per device and two each appear
in the top-edge banks, Bank 0 and 1, and the bottom-edge
banks, Banks 4 and 5. See
labeling.
During configuration, these pins behave exactly like
user-I/O pins.
Also see
CONFIG: Dedicated Configuration Pins
The dedicated configuration pins control the configuration
process and are not available as user-I/O pins. Every pack-
age has seven dedicated configuration pins. All CON-
FIG-type pins are powered by the +2.5V VCCAUX supply.
Also see
R
REF
40a.
40b. A resistor is not required for the VRN_# pin.
Global Clock Network, page
Configuration, page
(1%)
split
Spartan-3 FPGA Family: Pinout Descriptions
(c) Split termination
termination—such
One of eight
I/O Banks
VRN
VRP
Figure 38
45.
V CCO
for a picture of bank
Figure
41.
as
DS099-4_03_071304
R
R
REF
REF
HSTL_I_DCI,
(1%)
(1%)
40c. Neither
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