XC3S400-4FT256C Xilinx Inc, XC3S400-4FT256C Datasheet - Page 63

• Manufacturer Part Number: XC3S400-4FT256C
• Description: SEMI CONDUCTOR
• Manufacturer: Xilinx Inc

Specifications of XC3S400-4FT256C

• Case: BGA
• Dc: 04+

Table 35: DC Characteristics of User I/Os Using Single-Ended Standards (Continued)
DS099-3 (v2.2) May 25, 2007
Product Specification
98
Notes:
1.
2.
3.
4.
5.
6.
7.
LVCMOS33
LVDCI_33,
LVDCI_DV2_33
LVTTL
PCI33_3
SSTL18_I
SSTL18_I_DCI
SSTL18_II
SSTL2_I
SSTL2_I_DCI
SSTL2_II
SSTL2_II_DCI
(IOSTANDARD) and Current
The numbers in this table are based on the conditions set forth in
Descriptions of the symbols used in this table are as follows:
Tested according to the standard’s relevant specifications. When using the DCI version of a standard on a given I/O bank, that bank
will consume more power than if the non-DCI version had been used instead. The additional power is drawn for the purpose of
impedance-matching at the I/O pins. A portion of this power is dissipated in the two R
For the LVCMOS and LVTTL standards: the same V
All Dedicated output pins (CCLK, DONE, and TDO) as well as Dual-Purpose totem-pole output pins (D0-D7 and BUSY/DOUT)
exhibit the characteristics of LVCMOS25 with 12 mA drive and Fast slew rate. For information concerning the use of 3.3V signals,
see the
Tested according to the relevant PCI specifications. For more information, see "Virtex-II Pro and Spartan-3 3.3V PCI Reference
Design" (XAPP653).
The minimum usable V
I
I
V
V
V
V
V
V
V
OL
OH
Drive Attribute (mA)
OL
OH
IL
IH
CCO
REF
TT
(4)
Signal Standard
–
–
–
–
–
–
–
(7)
–
the input voltage that indicates a Low logic level
the output current condition under which V
the output current condition under which V
the input voltage that indicates a High logic level
–
the voltage applied to a resistor termination
the output voltage that indicates a Low logic level
the output voltage that indicates a High logic level
(4)
3.3V-Tolerant Configuration Interface, page
R
the reference voltage for setting the input switching threshold
the supply voltage for output drivers as well as LVCMOS, LVTTL, and PCI inputs
(7)
12
16
24
12
16
24
2
4
6
8
2
4
6
8
TT
voltage is 1.25V
Note 3
Note 3
Note 6
Note 3
Note 3
(mA)
13.4
16.2
I
6.7
8.1
12
16
24
12
16
24
OL
2
4
6
8
2
4
6
8
Test Conditions
OL
OH
is tested
OL
is tested
46.
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and V
OH
Spartan-3 FPGA Family: DC and Switching Characteristics
limits apply for both the Fast and Slow slew attributes.
Note 3
Note 6
Note 3
Note 3
Note 3
–13.4
–16.2
(mA)
Table 31
–6.7
–8.1
–12
–16
–24
–12
–16
–24
I
–2
–4
–6
–8
–2
–4
–6
–8
OH
and
Table
34.
REF
V
V
V
V
0.10V
TT
TT
Max (V)
TT
TT
resistors.
Logic Level Characteristics
V
0.4
0.4
- 0.475
- 0.475
- 0.61
- 0.80
OL
CCO
V
V
V
V
V
0.90V
TT
TT
TT
TT
Min (V)
CCO
V
2.4
+ 0.475
+ 0.475
+ 0.61
+ 0.80
OH
- 0.4
CCO
63