XC3S400-4FT256C Xilinx Inc, XC3S400-4FT256C Datasheet - Page 14

• Manufacturer Part Number: XC3S400-4FT256C
• Description: SEMI CONDUCTOR
• Manufacturer: Xilinx Inc

Specifications of XC3S400-4FT256C

• Case: BGA
• Dc: 04+

Spartan-3 FPGA Family: Functional Description
According to
CK inputs of the upper registers on the output and
three-state paths. Similarly, OTCLK2 connects the CK
inputs for the lower registers on the output and three-state
paths. The upper and lower registers on the input path have
independent clock lines: ICLK1 and ICLK2.
The enable line OCE connects the CE inputs of the upper
and lower registers on the output path. Similarly, TCE con-
nects the CE inputs for the register pair on the three-state
Table 5: Storage Element Options
Double-Data-Rate Transmission
Double-Data-Rate (DDR) transmission describes the tech-
nique of synchronizing signals to both the rising and falling
edges of the clock signal. Spartan-3 devices use regis-
ter-pairs in all three IOB paths to perform DDR operations.
The pair of storage elements on the IOB’s Output path
(OFF1 and OFF2), used as registers, combine with a spe-
cial multiplexer to form a DDR D-type flip-flop (FDDR). This
primitive permits DDR transmission where output data bits
are synchronized to both the rising and falling edges of a
clock. It is possible to access this function by placing either
an FDDRRSE or an FDDRCPE component or symbol into
the design. DDR operation requires two clock signals (50%
duty cycle), one the inverted form of the other. These sig-
nals trigger the two registers in alternating fashion, as
shown in
(DCM) generates the two clock signals by mirroring an
incoming signal, then shifting it 180 degrees. This approach
ensures minimal skew between the two signals.
The storage-element-pair on the Three-State path (TFF1
and TFF2) can also be combined with a local multiplexer to
form an FDDR primitive. This permits synchronizing the out-
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54
FF/Latch
SYNC/ASYNC
SRHIGH/SRLOW
INIT1/INIT0
Option Switch
Figure
Figure
6. Commonly, the Digital Clock Manager
5, the clock line OTCLK1 connects the
Chooses between an edge-sensitive flip-flop or
a level-sensitive latch
Determines whether SR is synchronous or
asynchronous
Determines whether SR acts as a Set, which
forces the storage element to a logic “1"
(SRHIGH) or a Reset, which forces a logic “0”
(SRLOW).
In the event of a Global Set/Reset, after
configuration or upon activation of the GSR net,
this switch decides whether to set or reset a
storage element. By default, choosing SRLOW
also selects INIT0; choosing SRHIGH also
selects INIT1.
Function
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path and ICE does the same for the register pair on the
input path.
The Set/Reset (SR) line entering the IOB is common to all
six registers, as is the Reverse (REV) line.
Each storage element supports numerous options in addi-
tion to the control over signal polarity described in the IOB
Overview section. These are described in
put enable to both the rising and falling edges of a clock.
This DDR operation is realized in the same way as for the
output path.
The storage-element-pair on the input path (IFF1 and IFF2)
allows an I/O to receive a DDR signal. An incoming DDR
clock signal triggers one register and the inverted clock sig-
nal triggers the other register. In this way, the registers take
turns capturing bits of the incoming DDR data signal.
Aside from high bandwidth data transfers, DDR can also be
used to reproduce, or “mirror”, a clock signal on the output.
This approach is used to transmit clock and data signals
together. A similar approach is used to reproduce a clock
signal at multiple outputs. The advantage for both
approaches is that skew across the outputs will be minimal.
Some adjacent I/O blocks (IOBs) share common routing
connecting the ICLK1, ICLK2, OTCLK1, and OTCLK2 clock
inputs of both IOBs. These IOB pairs are identified by their
differential pair names IO_LxxN_# and IO_LxxP_#, where
"xx" is an I/O pair number and ‘#’ is an I/O bank number.
Two adjacent IOBs containing DDR registers must share
common clock inputs, otherwise one or more of the clock
signals will be unroutable.
Independent for each storage element.
Independent for each storage element.
Independent for each storage element, except
when using FDDR. In the latter case, the selection
for the upper element (OFF1 or TFF2) applies to
both elements.
Independent for each storage element, except
when using FDDR. In the latter case, selecting
INIT0 for one element applies to both elements
(even though INIT1 is selected for the other).
Specificity
DS099-2 (v2.2) May 25, 2007
Product Specification
Table
5.
R