XC3S400-4FT256C Xilinx Inc, XC3S400-4FT256C Datasheet - Page 208

• Manufacturer Part Number: XC3S400-4FT256C
• Description: SEMI CONDUCTOR
• Manufacturer: Xilinx Inc

Specifications of XC3S400-4FT256C

• Case: BGA
• Dc: 04+

Spartan-3 FPGA Family: Pinout Descriptions
Revision History
208
04/26/06
05/25/07
04/03/03
04/21/03
05/12/03
07/11/03
07/29/03
08/19/03
10/09/03
12/17/03
02/27/04
07/13/04
08/24/04
01/17/05
08/19/05
04/03/06
Date
Version No.
1.1.1
1.1.2
1.2.1
1.2.2
1.5.1
2.1
2.2
1.0
1.1
1.2
1.3
1.4
1.5
1.6
1.7
2.0
Initial Xilinx release.
Added information on the VQ100 package footprint, including a complete pinout table
Updated
Added clarifying comments to HSWAP_EN pin description on
in
and
AM32 pin was missing GND label in FG1156 package diagram
Corrected misspellings of GCLK in
During Configuration
square in
Corrected pin names on FG1156 package. Some package balls incorrectly included LVDS pair names. The affected balls on the
FG1156 package include G1, G2, G33, G34, U9, U10, U25, U26, V9, V10, V25, V26, AH1, AH2, AH33, AH34. The number of LVDS
pairs is unaffected. Modified affected balls and re-sorted rows in
and Excel electronic versions of FG1156 pinout.
Removed 100 MHz ConfigRate option in
output in
Some pins had incorrect bank designations and were improperly sorted in
DCI_IN to DCI and added black diamond to N.C. pins in
corrected spelling of pins 45, 48, and 81.
Added FG320 pin tables and pinout diagram
footprint
wording in
Clarified wording in
maximum I/O values for the FG676, FG900, and FG1156 packages.
Added information on lead-free (Pb-free) package options to the
VRN_# reference resistor requirements for I/O standards that use single termination as described in the
section and in
Removed XC3S2000 references from
Added XC3S50 in CP132 package option. Added XC3S2000 in FG456 package option. Added XC3S4000 in FG676 package option.
Added
Table
Removed term “weak” from the description of pull-up and pull-down resistors. Added
precautions to
Added
dedicated pull-up resistors during configuration, regardless of the HSWAP_EN value to
Configuration. Updated
Corrected swapped data row in
swapped with the Theta-JC column. Made additional notations on CONFIG and JTAG pins that
have pull-up resistors during configuration, regardless of the HSWAP_EN input.
Added link on
Added Note 1 to
Figure 50a
Figure
99,
Package Thermal
Selecting the Right Package Option
(Figure
Table 84
Table
Table
Table
Precautions When Using the JTAG Port in 3.3V Environments
41. Updated Xilinx hypertext links. Added XC3S200 and XC3S400 to Pin Name column in
and
Figure
CCLK: Configuration Clock
76.
101,
109, key, and package drawing.
44), the PQ208 footprint
Figure
with final I/O counts for the VQ100 package. Also added final differential I/O pair counts for the TQ144 package.
Using JTAG Port After Configuration
page 119
Table
40b. Graduated from Advance Product Specification to Product Specification.
section. Clarified references to Module 2. For XC3S5000 in FG1156 package, corrected N.C. symbol to a black
Table 102
50b. Some thick lines separating I/O banks were incorrect. Made cosmetic changes to
Precautions When Using the JTAG Port in 3.3V
Characteristics. Updated
102,
Table
to Material Declaration Data Sheets. Corrected units typo in
Table 68
www.xilinx.com
105,
FG1156: 1156-lead Fine-pitch Ball Grid
about VREF for XC3S1500 in FG676.
CCLK: Configuration Clock
(Figure
Figure
and
and indicated that CCLK should be treated as an I/O during Master mode in
(FG320: 320-lead Fine-pitch Ball Grid
Table
section. Modified or added
Table
45), the FG676 footprint
43, and
Figure 39
85. The Theta-JA with zero airflow column was
69. Changed CMOS25 to LVCMOS25 in
Table
Description
Figure
section. In
page
to make it a more obvious example. Added detail about which pins have
92. In
(Figure
Package Overview
Table
49.
111. Updated the footprint diagram for the FG900 package shown
Figure
109. Updated affected balls in
Table
section and in
51).
Table
(Figure
Table
45, removed some extraneous text from pin 106 and
Environments.
80, reduced package height for FG320 and increased
section.
80,
Array.
92. No pin names or functions changed. Renamed
49), and the FG900 footprint
Table
IDCODE Register
section plus
Array). Made cosmetic changes to the TQ144
Table
(Table
Table 69
82,
79. Added note that TDO is a totem-pole
86) and footprint diagram
Table
DS099-4 (v2.2) May 25, 2007
Dual-Purpose Pin I/O Standard
and to
Table 80
83,
Figure
Table
Table
values. Added signal integrity
Pin Behavior During
Product Specification
DCI Termination Types
and
90.
51. Also updated ASCII
84,
Table
(Figure
Figure
Table
82. Clarified the
38,
(Figure
50). Clarified
88,
Table
Table
Figure
Table
42).
78.
73.
89,
40,
R