FPGA, VIRTEX-5 LXT, 50K, 665FCBGA

XC5VLX50T-1FFG665C

Manufacturer Part NumberXC5VLX50T-1FFG665C
DescriptionFPGA, VIRTEX-5 LXT, 50K, 665FCBGA
ManufacturerXilinx Inc
SeriesVirtex™-5 LXT
XC5VLX50T-1FFG665C datasheets
Product Change Notification
 


Specifications of XC5VLX50T-1FFG665C

No. Of Logic Blocks7200Family TypeVirtex-5
No. Of Speed Grades1Total Ram Bits2211840
No. Of I/o's360Clock ManagementDCM, PLL
I/o Supply Voltage3.3VOperating Frequency Max550MHz
Number Of Logic Elements/cells46080Number Of Labs/clbs3600
Number Of I /o360Voltage - Supply0.95 V ~ 1.05 V
Mounting TypeSurface MountOperating Temperature0°C ~ 85°C
Package / Case665-BBGA, FCBGACore Supply Voltage Range1V
Rohs CompliantYesLead Free Status / RoHS StatusLead free / RoHS Compliant
For Use WithHW-V5-ML561-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML550-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML521-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5GBE-DK-UNI-G - KIT DEV V5 LXT GIGABIT ETHERNET122-1508 - EVALUATION PLATFORM VIRTEX-5Number Of Gates-
Other names122-1565  
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Page 17/91

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Table 33: GTP_DUAL Tile User Clock Switching Characteristics
Symbol
Description
F
TXOUTCLK maximum frequency
TXOUT
F
RXRECCLK maximum frequency
RXREC
T
RXUSRCLK maximum frequency
RX
T
RXUSRCLK2 maximum frequency
RX2
T
TXUSRCLK maximum frequency
TX
T
TXUSRCLK2 maximum frequency
TX2
Notes:
1.
Clocking must be implemented as described in UG196: Virtex-5 FPGA RocketIO GTP Transceiver User Guide
Table 34: GTP_DUAL Tile Transmitter Switching Characteristics
Symbol
F
Serial data rate range
GTPTX
T
TX Rise time
RTX
T
TX Fall time
FTX
T
TX lane-to-lane skew
LLSKEW
V
Electrical idle amplitude
TXOOBVDPP
T
Electrical idle transition time
TXOOBTRANS
(2)
T
Total Jitter
J3.75
D
Deterministic Jitter
J3.75
(2)
T
Total Jitter
J3.2
D
Deterministic Jitter
J3.2
(2)
T
Total Jitter
J2.5
D
Deterministic Jitter
J2.5
(2)
T
Total Jitter
J2.0
D
Deterministic Jitter
J2.0
(2)
T
Total Jitter
J1.25
D
Deterministic Jitter
J1.25
(2)
T
Total Jitter
J1.00
D
Deterministic Jitter
J1.00
(2)
T
Total Jitter
J500
D
Deterministic Jitter
J500
(2)
T
Total Jitter
J100
D
Deterministic Jitter
J100
Notes:
1.
Using same REFCLK input with TXENPMAPHASEALIGN enabled for up to four consecutive GTP_DUAL sites.
2.
Using PLL_DIVSEL_FB = 2, INTDATAWIDTH = 1.
3.
All jitter values are based on a Bit-Error Ratio of 1e
DS202 (v5.3) May 5, 2010
Product Specification
Virtex-5 FPGA Data Sheet: DC and Switching Characteristics
(1)
Conditions
RXDATAWIDTH = 0
RXDATAWIDTH = 1
TXDATAWIDTH = 0
TXDATAWIDTH = 1
Description
(1)
3.75 Gb/s
(2)
3.20 Gb/s
(2)
2.50 Gb/s
(2)
2.00 Gb/s
(2)
1.25 Gb/s
(2)
1.00 Gb/s
(2)
500 Mb/s
(2)
100 Mb/s
(2)
–12
.
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Speed Grade
Units
-3
-2
-1
375
375
320
MHz
375
375
320
MHz
375
375
320
MHz
350
350
320
MHz
187.5
187.5
160
MHz
375
375
320
MHz
350
350
320
MHz
187.5
187.5
160
MHz
Min
Typ
Max
Units
0.1
F
Gb/s
GTPMAX
140
ps
120
ps
855
ps
20
mV
40
ns
0.35
UI
0.19
UI
0.35
UI
0.19
UI
0.30
UI
0.14
UI
0.30
UI
0.14
UI
0.20
UI
0.10
UI
0.20
UI
0.10
UI
0.10
UI
0.04
UI
0.02
UI
0.01
UI
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