FPGA, VIRTEX-5 LXT, 50K, 665FCBGA

XC5VLX50T-1FFG665C

Manufacturer Part NumberXC5VLX50T-1FFG665C
DescriptionFPGA, VIRTEX-5 LXT, 50K, 665FCBGA
ManufacturerXilinx Inc
SeriesVirtex™-5 LXT
XC5VLX50T-1FFG665C datasheets
Product Change Notification
 


Specifications of XC5VLX50T-1FFG665C

No. Of Logic Blocks7200Family TypeVirtex-5
No. Of Speed Grades1Total Ram Bits2211840
No. Of I/o's360Clock ManagementDCM, PLL
I/o Supply Voltage3.3VOperating Frequency Max550MHz
Number Of Logic Elements/cells46080Number Of Labs/clbs3600
Number Of I /o360Voltage - Supply0.95 V ~ 1.05 V
Mounting TypeSurface MountOperating Temperature0°C ~ 85°C
Package / Case665-BBGA, FCBGACore Supply Voltage Range1V
Rohs CompliantYesLead Free Status / RoHS StatusLead free / RoHS Compliant
For Use WithHW-V5-ML561-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML550-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML521-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5GBE-DK-UNI-G - KIT DEV V5 LXT GIGABIT ETHERNET122-1508 - EVALUATION PLATFORM VIRTEX-5Number Of Gates-
Other names122-1565  
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Date
Version
05/18/07
3.1
• Added typical values for n and r in
• Revised and added values to
• Revised standard I/O levels in
• Additions and updates to
and
Table
• Added
• Changed the design software version that matches this data sheet above
• Added new section:
• In
Switching
• LVTTL, Slow and Fast, 2 mA, 4 mA, and 6 mA
• LVCMOS33, Slow and Fast, 2 mA, 4 mA, and 6 mA
• LVCMOS25, Slow and Fast, 2 mA and 4 mA, and Fast 12 mA
• LVCMOS18, Slow and Fast, 2 mA, 4 mA, and 6 mA
• LVCMOS15 and LVCMOS12, Slow and Fast, 2 mA
• T
IDOCK
• Setup/Hold for Control Lines and Data Lines in
• Add T
• Revised T
• Replaced T
• Revised T
• Revised T
• Revised Hold Times of Data/Control Pins to the Input Register Clock.
Setup/Hold times of {PCIN, CARRYCASCIN, MULTSIGNIN} input to P register CLK. Hold times of
some of the CE pins. Hold times of some of the RST pins. Hold times of {A, B} input to {P,
CARRYOUT} output using multiplier and {ACIN, BCIN} input to {P, CARRYOUT} output using
multiplier, CLK (AREG, BREG) to {P, CARRYOUT} output using multiplier, in
• Updated and added values to
• Revised -1 speed F
• Added Note 4 to T
• Added ± values to
• In
Virtex-5 Device Pin-to-Pin Output Parameter
• Revised values in
• In
Virtex-5 Device Pin-to-Pin Input Parameter
• Revised values in
• In
Source-Synchronous Switching
• Revised values in
• Added package skew values to
• Revised values in
06/15/07
3.2
• Updated T
• Corrected V
• Changed the design software version that matches this data sheet above
• Added
• Added T
• In
Virtex-5 Device Pin-to-Pin Output Parameter
Table
• In
Virtex-5 Device Pin-to-Pin Input Parameter
• Corrected units to ns in
DS202 (v5.3) May 5, 2010
Product Specification
Virtex-5 FPGA Data Sheet: DC and Switching Characteristics
Revision
Table
3.
Table
4.
Table
7.
Table
26,
Table
28,
Table
35.
Ethernet MAC Switching Characteristics, page
I/O Standard Adjustment Measurement Methodology, page
Characteristics, the following values are revised:
and T
in
Table
60.
IDOCKD
and revised T
IDELAYPAT_JIT
IDELAYRESOLUTION
page 45
and removed T
RCK
CKSR
with T
symbol in
Table 66, page
TWC
MCP
in
Table
67.
CECK
and T
RCKO_FLAGS
RDCK_DI_ECC
Table 70, page
value in
Table 72, page
MAX
and revised F
LOCKMAX
INDUTY
Table 79
and
Table
80. Changed T
Table 84
through
Table
90.
Table 91
through
Table
97.
Characteristics:
Table 98, page
83.
Table 99, page
Table 101, page
85.
in
Table
1.
STG
/V
in
Table 9
and
Table 10, page
OH
OL
Production Silicon and ISE Software Status, page
and revised T
IODELAY_CLK_MAX
CKSR
90.
Table 98, page
83.
www.xilinx.com
29,
Table
30,
Table
48,
Table
32,
Table
25.
Table 54
on
37.
(Table
56).
(Table
56).
(Table
56).
(Table
56).
(Table
56).
Table
62.
in
Table 64, page 44
and added Notes 1 and 2.
Table 65, page
44.
46.
encode only in
Table
68.
Table
51.
53.
, F
,and F
in
Table 74, page
INMAX
VCOMAX
in
Table
80.
OUT_OFFSET
Guidelines:
Guidelines:
84.
8.
Table 54
on
31.
in
Table 64, page
44.
Guidelines: Revised values in
Table 85
Guidelines: Revised values in
Table 92
33,
Table
34,
page
30.
69.
55.
page
30.
through
through
Table
97.
88