FPGA, VIRTEX-5 LXT, 50K, 665FCBGA

XC5VLX50T-1FFG665C

Manufacturer Part NumberXC5VLX50T-1FFG665C
DescriptionFPGA, VIRTEX-5 LXT, 50K, 665FCBGA
ManufacturerXilinx Inc
SeriesVirtex™-5 LXT
XC5VLX50T-1FFG665C datasheets
Product Change Notification
 


Specifications of XC5VLX50T-1FFG665C

No. Of Logic Blocks7200Family TypeVirtex-5
No. Of Speed Grades1Total Ram Bits2211840
No. Of I/o's360Clock ManagementDCM, PLL
I/o Supply Voltage3.3VOperating Frequency Max550MHz
Number Of Logic Elements/cells46080Number Of Labs/clbs3600
Number Of I /o360Voltage - Supply0.95 V ~ 1.05 V
Mounting TypeSurface MountOperating Temperature0°C ~ 85°C
Package / Case665-BBGA, FCBGACore Supply Voltage Range1V
Rohs CompliantYesLead Free Status / RoHS StatusLead free / RoHS Compliant
For Use WithHW-V5-ML561-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML550-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML521-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5GBE-DK-UNI-G - KIT DEV V5 LXT GIGABIT ETHERNET122-1508 - EVALUATION PLATFORM VIRTEX-5Number Of Gates-
Other names122-1565  
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CLB Distributed RAM Switching Characteristics (SLICEM Only)
Table 66: CLB Distributed RAM Switching Characteristics
Symbol
Sequential Delays
T
Clock to A – B outputs
SHCKO
T
Clock to AMUX – BMUX outputs
SHCKO_1
Setup and Hold Times Before/After Clock CLK
T
/T
A – D inputs to CLK
DS
DH
T
/T
Address An inputs to clock
AS
AH
T
/T
WE input to clock
WS
WH
T
/T
CE input to CLK
CECK
CKCE
Clock CLK
T
Minimum pulse width
MPW
T
Minimum clock period
MCP
Notes:
1.
A Zero “0” Hold Time listing indicates no hold time or a negative hold time. Negative values cannot be guaranteed “best-case”, but if a “0” is
listed, there is no positive hold time.
2.
TSHCKO also represents the CLK to XMUX output. Refer to TRACE report for the CLK to XMUX path.
CLB Shift Register Switching Characteristics (SLICEM Only)
Table 67: CLB Shift Register Switching Characteristics
Symbol
Sequential Delays
T
Clock to A – D outputs
REG
T
Clock to AMUX – DMUX output
REG_MUX
T
Clock to DMUX output via M31 output
REG_M31
Setup and Hold Times Before/After Clock CLK
T
/T
WE input
WS
WH
T
/T
CE input to CLK
CECK
CKCE
T
/T
A – D inputs to CLK
DS
DH
Clock CLK
T
Minimum pulse width
MPW
Notes:
1.
A Zero “0” Hold Time listing indicates no hold time or a negative hold time. Negative values cannot be guaranteed “best-case”, but if a “0” is
listed, there is no positive hold time.
DS202 (v5.3) May 5, 2010
Product Specification
Virtex-5 FPGA Data Sheet: DC and Switching Characteristics
Description
Description
www.xilinx.com
Speed Grade
Units
-3
-2
-1
1.08
1.26
1.54
ns, Max
1.19
1.38
1.68
ns, Max
0.72
0.84
1.03
ns, Min
0.20
0.22
0.26
0.41
0.46
0.54
ns, Min
0.20
0.22
0.27
0.34
0.39
0.46
ns, Min
–0.06
–0.04
–0.02
0.36
0.42
0.51
ns, Min
–0.08
–0.07
–0.06
0.70
0.82
1.00
ns, Min
1.40
1.64
2.00
ns, Min
Speed Grade
Units
-3
-2
-1
1.23
1.43
1.73
Max
1.33
1.55
1.87
Max
0.99
1.15
1.38
Max
0.21
0.24
0.29
ns, Min
–0.06
–0.04
–0.02
0.23
0.27
0.33
ns, Min
–0.08
–0.07
–0.06
0.57
0.66
0.78
ns, Min
0.07
0.09
0.11
0.60
0.70
0.85
ns, Min
ns,
ns,
ns,
46