XC5VLX50T-1FFG665C Xilinx Inc, XC5VLX50T-1FFG665C Datasheet - Page 26

FPGA, VIRTEX-5 LXT, 50K, 665FCBGA

XC5VLX50T-1FFG665C

Manufacturer Part Number
XC5VLX50T-1FFG665C
Description
FPGA, VIRTEX-5 LXT, 50K, 665FCBGA
Manufacturer
Xilinx Inc
Series
Virtex™-5 LXTr

Specifications of XC5VLX50T-1FFG665C

No. Of Logic Blocks
7200
Family Type
Virtex-5
No. Of Speed Grades
1
Total Ram Bits
2211840
No. Of I/o's
360
Clock Management
DCM, PLL
I/o Supply Voltage
3.3V
Operating Frequency Max
550MHz
Number Of Logic Elements/cells
46080
Number Of Labs/clbs
3600
Number Of I /o
360
Voltage - Supply
0.95 V ~ 1.05 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
665-BBGA, FCBGA
Core Supply Voltage Range
1V
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
HW-V5-ML561-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML550-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML521-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5GBE-DK-UNI-G - KIT DEV V5 LXT GIGABIT ETHERNET122-1508 - EVALUATION PLATFORM VIRTEX-5
Number Of Gates
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Other names
122-1565
System Monitor Analog-to-Digital Converter Specification
Table 51: Analog-to-Digital Specifications
Parameter
Symbol
AV
= 2.5V ± 2%, V
= 2.5V, V
DD
REFP
REFN
DC Accuracy: All external input channels such as V
and Common Mode = 0V
Resolution
Integral Nonlinearity
INL
Differential Nonlinearity
DNL
(1)
Unipolar Offset Error
(1)
Bipolar Offset Error
(1)
Gain Error
(1)
Bipolar Gain Error
Total Unadjusted Error
TUE
(Uncalibrated)
Total Unadjusted Error
TUE
(Calibrated)
Calibrated Gain Temperature
Coefficient
DC Common-Mode Reject
CMRR
(2)
Conversion Rate
Conversion Time - Continuous
t
CONV
Conversion Time - Event
t
CONV
T/H Acquisition Time
t
ACQ
DRP Clock Frequency
DCLK
ADC Clock Frequency
ADCCLK
CLK Duty cycle
(3)
Analog Inputs
Dedicated Analog Inputs
Input Voltage Range
V
- V
P
N
Auxiliary Analog Inputs
Input Voltage Range
V
/V
to V
AUXP[0]
AUXN[0]
AUXP[15]
/V
AUXN[15]
Input Leakage Current
Input Capacitance
On-chip Supply Monitor Error
On-chip Temperature Monitor
Error
DS202 (v5.3) May 5, 2010
Product Specification
Virtex-5 FPGA Data Sheet: DC and Switching Characteristics
Comments/Conditions
= 0V, ADCCLK = 5.2 MHz, T
= T
to T
A
MIN
/V
and V
[15:0]/V
P
N
AUXP
AUXN
No missing codes (T
to T
)
MIN
MAX
Guaranteed Monotonic
Uncalibrated
Uncalibrated measured in bipolar mode
Uncalibrated
Uncalibrated measured in bipolar mode
Deviation from ideal transfer function.
=
V
– V
2.5V
REFP
REFN
Deviation from ideal transfer function.
=
V
– V
2.5V
REFP
REFN
Variation of FS code with temperature
=
V
= V
0.5V ± 0.5V,
DC
N
CM
=
V
– V
100mV
P
N
Number of CLK cycles
Number of CLK cycles
Number of CLK cycles
DRP clock frequency
Derived from DCLK
Unipolar Operation
Differential Inputs
Unipolar Common Mode Range (FS input)
Differential Common Mode Range (FS input)
Bandwidth
Unipolar Operation
Differential Operation
Unipolar Common Mode Range (FS input)
Differential Common Mode Range (FS input)
Bandwidth
A/D not converting, ADCCLK stopped
V
and V
with calibration enabled
CCINT
CCAUX
–40°C to +125°C with calibration enabled
www.xilinx.com
Min
Typ
Max
, Typical values at T
=+25°C
MAX
A
[15:0], Unipolar Mode,
10
±2
±0.9
±2
±30
±2
±30
±0.2
±2
±0.2
±2
±10
±1
±2
±0.01
70
26
32
21
4
8
250
1
5.2
40
60
0
1
–0.25
+0.25
0
+0.5
+0.3
+0.7
20
0
1
–0.25
+0.25
0
+0.5
+0.3
+0.7
10
±1.0
10
±1.0
±4
Units
Bits
LSBs
LSBs
LSBs
LSBs
%
%
LSBs
LSBs
LSB/°C
dB
MHz
MHz
%
Volts
MHz
Volts
kHz
µA
pF
% Reading
°C
26

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