FPGA, VIRTEX-5 LXT, 50K, 665FCBGA

XC5VLX50T-1FFG665C

Manufacturer Part NumberXC5VLX50T-1FFG665C
DescriptionFPGA, VIRTEX-5 LXT, 50K, 665FCBGA
ManufacturerXilinx Inc
SeriesVirtex™-5 LXT
XC5VLX50T-1FFG665C datasheets
Product Change Notification
 


Specifications of XC5VLX50T-1FFG665C

No. Of Logic Blocks7200Family TypeVirtex-5
No. Of Speed Grades1Total Ram Bits2211840
No. Of I/o's360Clock ManagementDCM, PLL
I/o Supply Voltage3.3VOperating Frequency Max550MHz
Number Of Logic Elements/cells46080Number Of Labs/clbs3600
Number Of I /o360Voltage - Supply0.95 V ~ 1.05 V
Mounting TypeSurface MountOperating Temperature0°C ~ 85°C
Package / Case665-BBGA, FCBGACore Supply Voltage Range1V
Rohs CompliantYesLead Free Status / RoHS StatusLead free / RoHS Compliant
For Use WithHW-V5-ML561-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML550-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML521-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5GBE-DK-UNI-G - KIT DEV V5 LXT GIGABIT ETHERNET122-1508 - EVALUATION PLATFORM VIRTEX-5Number Of Gates-
Other names122-1565  
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Block RAM and FIFO Switching Characteristics
Table 68: Block RAM and FIFO Switching Characteristics
Symbol
Block RAM and FIFO Clock to Out Delays
(1)
T
and T
Clock CLK to DOUT output (without output
RCKO_DO
RCKO_DOR
register)
Clock CLK to DOUT output (with output register)
Clock CLK to DOUT output with ECC (without output
register)
Clock CLK to DOUT output with ECC (with output
register)
Clock CLK to DOUT output with Cascade (without
output register)
Clock CLK to DOUT output with Cascade (with output
register)
T
Clock CLK to FIFO flags outputs
RCKO_FLAGS
T
Clock CLK to FIFO pointer outputs
RCKO_POINTERS
T
Clock CLK to BITERR (with output register)
RCKO_ECCR
T
Clock CLK to BITERR (without output register)
RCKO_ECC
Clock CLK to ECCPARITY in standard ECC mode
Clock CLK to ECCPARITY in ECC encode only mode
Setup and Hold Times Before/After Clock CLK
T
/T
ADDR inputs
RCCK_ADDR
RCKC_ADDR
T
/T
DIN inputs
RDCK_DI
RCKD_DI
T
/T
DIN inputs with ECC in standard mode
RDCK_DI_ECC
RCKD_DI_ECC
DIN inputs with ECC encode only
T
/T
Block RAM Enable (EN) input
RCCK_EN
RCKC_EN
T
/T
CE input of output register
RCCK_REGCE
RCKC_REGCE
T
/T
Synchronous Set/ Reset (SSR) input
RCCK_SSR
RCKC_SSR
T
/T
Write Enable (WE) input
RCCK_WE
RCKC_WE
T
/T
WREN/RDEN FIFO inputs
RCCK_WREN
RCKC_WREN
DS202 (v5.3) May 5, 2010
Product Specification
Virtex-5 FPGA Data Sheet: DC and Switching Characteristics
Description
(2,3)
(2,3)
(4,5)
(2)
(4)
(6)
(7)
(8)
(9)
(9)
(9
(10)
www.xilinx.com
Speed Grade
-3
-2
-1
1.79
1.92
2.19
(4,5)
0.61
0.69
0.82
2.64
3.03
3.61
0.66
0.77
0.93
2.10
2.44
2.94
0.91
1.07
1.30
0.76
0.87
1.02
1.10
1.26
1.48
0.66
0.77
0.93
2.48
2.85
3.41
1.29
1.47
1.74
0.77
0.89
1.05
0.34
0.40
0.48
0.30
0.32
0.36
0.27
0.30
0.35
0.28
0.28
0.29
0.33
0.37
0.42
0.32
0.33
0.36
0.68
0.72
0.77
0.32
0.33
0.36
0.32
0.36
0.42
0.15
0.15
0.15
0.15
0.16
0.18
0.22
0.24
0.27
0.17
0.21
0.26
0.23
0.25
0.28
0.44
0.51
0.63
0.16
0.17
0.18
0.36
0.41
0.48
0.30
0.34
0.40
Units
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Min
ns, Min
ns, Min
ns, Min
ns, Min
ns, Min
ns, Min
ns, Min
ns, Min
47