FPGA, VIRTEX-5 LXT, 50K, 665FCBGA

XC5VLX50T-1FFG665C

Manufacturer Part NumberXC5VLX50T-1FFG665C
DescriptionFPGA, VIRTEX-5 LXT, 50K, 665FCBGA
ManufacturerXilinx Inc
SeriesVirtex™-5 LXT
XC5VLX50T-1FFG665C datasheets
Product Change Notification
 


Specifications of XC5VLX50T-1FFG665C

No. Of Logic Blocks7200Family TypeVirtex-5
No. Of Speed Grades1Total Ram Bits2211840
No. Of I/o's360Clock ManagementDCM, PLL
I/o Supply Voltage3.3VOperating Frequency Max550MHz
Number Of Logic Elements/cells46080Number Of Labs/clbs3600
Number Of I /o360Voltage - Supply0.95 V ~ 1.05 V
Mounting TypeSurface MountOperating Temperature0°C ~ 85°C
Package / Case665-BBGA, FCBGACore Supply Voltage Range1V
Rohs CompliantYesLead Free Status / RoHS StatusLead free / RoHS Compliant
For Use WithHW-V5-ML561-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML550-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML521-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5GBE-DK-UNI-G - KIT DEV V5 LXT GIGABIT ETHERNET122-1508 - EVALUATION PLATFORM VIRTEX-5Number Of Gates-
Other names122-1565  
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LVPECL DC Specifications (LVPECL_25)
These values are valid when driving a 100Ω differential load only, i.e., a 100Ω resistor between the two receiver pins. The
V
levels are 200 mV below standard LVPECL levels and are compatible with devices tolerant of lower common-mode
OH
ranges.
Table 11
summarizes the DC output specifications of LVPECL. For more information on using LVPECL
Virtex-5 FPGA User Guide, Chapter 6, SelectIO Resources.
Table 11: LVPECL DC Specifications
Symbol
DC Parameter
V
Output High Voltage
OH
V
Output Low Voltage
OL
V
Input Common-Mode Voltage
ICM
V
Differential Input Voltage
IDIFF
Notes:
1.
Recommended input maximum voltage not to exceed V
2.
Recommended input minimum voltage not to go below –0.5V.
PowerPC 440 Switching Characteristics
Consult the Embedded Processor Block in Virtex-5 FPGAs Reference Guide for further information.
Table 12: Processor Block Switching Characteristics
Clock Name
CPMC440CLK
CPMINTERCONNECTCLK
CPMPPCS0PLBCLK
CPMPPCS1PLBCLK
CPMPPCMPLBCLK
CPMMCCLK
CPMFCMCLK
CPMDCRCLK
CPMDMA0LLCLK
CPMDMA1LLCLK
CPMDMA2LLCLK
CPMDMA3LLCLK
JTGC440TCK
CPMC440TIMERCLOCK
Notes:
1.
Typical bus frequencies are provided for reference only, actual frequencies are user-design dependent.
2.
Refer to
DS567
for maximum clock speed of designs using the DDR2 Memory Controller for PowerPC® 440 Processors.
DS202 (v5.3) May 5, 2010
Product Specification
Virtex-5 FPGA Data Sheet: DC and Switching Characteristics
Min
V
– 1.025
CC
V
– 1.81
CC
0.6
(1,2)
0.100
+ 0.2V.
CCO
Description
CPU clock
Xbar clock
(1)
Slave 0 PLB clock
(1)
Slave 1 PLB clock
(1)
Master PLB clock
(1)(2)
Memory interface clock
(1)
FCM clock
(1)
FPGA logic DCR clock
(1)
DMA0 LL clock
(1)
DMA1 LL clock
(1)
DMA2 LL clock
(1)
DMA3 LL clock
JTAG clock
Timer clock
www.xilinx.com
,
see UG190:
Typ
Max
Units
1.545
V
– 0.88
V
CC
0.795
V
– 1.62
V
CC
2.2
V
1.5
V
Speed Grade
Units
-3
-2
-1
550
475
400
MHz
366.6
316.6
266.6
MHz
183.3
158.3
133.3
MHz
183.3
158.3
133.3
MHz
183.3
158.3
133.3
MHz
366.6
316.6
266.6
MHz
275
237.5
200
MHz
183.3
158.3
133.3
MHz
250
250
200
MHz
250
250
200
MHz
250
250
200
MHz
250
250
200
MHz
50
50
50
MHz
275
237.5
200
MHz
9