FPGA, VIRTEX-5 LXT, 50K, 665FCBGA

XC5VLX50T-1FFG665C

Manufacturer Part NumberXC5VLX50T-1FFG665C
DescriptionFPGA, VIRTEX-5 LXT, 50K, 665FCBGA
ManufacturerXilinx Inc
SeriesVirtex™-5 LXT
XC5VLX50T-1FFG665C datasheets
Product Change Notification
 


Specifications of XC5VLX50T-1FFG665C

No. Of Logic Blocks7200Family TypeVirtex-5
No. Of Speed Grades1Total Ram Bits2211840
No. Of I/o's360Clock ManagementDCM, PLL
I/o Supply Voltage3.3VOperating Frequency Max550MHz
Number Of Logic Elements/cells46080Number Of Labs/clbs3600
Number Of I /o360Voltage - Supply0.95 V ~ 1.05 V
Mounting TypeSurface MountOperating Temperature0°C ~ 85°C
Package / Case665-BBGA, FCBGACore Supply Voltage Range1V
Rohs CompliantYesLead Free Status / RoHS StatusLead free / RoHS Compliant
For Use WithHW-V5-ML561-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML550-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML521-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5GBE-DK-UNI-G - KIT DEV V5 LXT GIGABIT ETHERNET122-1508 - EVALUATION PLATFORM VIRTEX-5Number Of Gates-
Other names122-1565  
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
Page 81
82
Page 82
83
Page 83
84
Page 84
85
Page 85
86
Page 86
87
Page 87
88
Page 88
89
Page 89
90
Page 90
91
Page 89/91

Download datasheet (3Mb)Embed
PrevNext
Date
Version
06/26/07
3.3
• Added conditions to DV
• Changed the F
• Updated GTP maximum line rates to 3.75 Gb/s in
• Updated maximum frequencies in
• Added 3.75 Gb/s condition and changed maximum value of F
• Added 3.75 Gb/s sinusoidal jitter specification and changed maximum value of F
page
18.
• Changed analog input common mode ranges in
• Changed T
07/26/07
3.4
• Added maximum value of I
• Revised
• In
Table 64, page
• In
Table 70, page
• Added Note 4 to T
• In
Virtex-5 Device Pin-to-Pin Input Parameter
09/27/07
3.5
• Added I
• Added
units for gain error and bipolar gain error.
• Removed unsupported XC5VSX95T -3 speed grade from
• Removed unsupported I/O standards (LVDS_33, LVDSEXT_33, and ULVDS_25) from
updated LVDSEXT, 2.5V in
• Added values to
Table
• In
Virtex-5 Device Pin-to-Pin Input Parameter
11/05/07
3.6
• Removed note 1 from
• Revised DDR2 memory interface performance in
• Revised
• Removed XC5VSX95T -3 speed grade support from applicable tables.
• Removed unsupported I/O standard (LVPECL_33) from
• Added T
• Revised note 3 in
• Clarified notes in
• Revised note 1 in
12/11/07
3.7
• Added new devices (XC5VLX20T, XC5VLX155, and XC5VLX155T) throughout document.
• Removed -3 speed grade from XC5VSX95T device lists.
• Added
• Revised
Virtex-5 Device Pin-to-Pin Input Parameter Guidelines
revised Note 1 on
• Revised Note 1 on
02/05/08
3.8
• Updated date on version 3.7. Other minor typographical edits.
• Updated the sentence: Xilinx does not specify the current or I/O behavior for other power-on sequences,
on
page
• Added values and notes to
Combined I
• Revised T
• Revised R
• Revised -2 performance value for SPI-4.2 in
• Added T
• Split out the F
devices in both tables.
• Added
• Updated
• Revised Note 1 on
DS202 (v5.3) May 5, 2010
Product Specification
Virtex-5 FPGA Data Sheet: DC and Switching Characteristics
Revision
in
Table 28, page
PPIN
symbol name to F
GTXMAX
GTPMAX
Table 33, page
values in
Table 99, page
PKGSKEW
to
Table 3, page
REF
Table 54
and changed the design software version in
44, added High Performance Mode to Note 2.
51, revised description of T
frequency range in
DUTYCYCRANGE_200_400
value and Note 2 to
Table
3.
BATT
DRP Clock Frequency
and Note 4 to
Table
Table
59.
Dynamic Reconfiguration Port (DRP) for DCM and PLL Before and After DCLK
70.
Table 52, page
28. F
MAX
Table 55
to add ISE 9.2i SP3 where applicable.
and T
to
Table 70, page
SMCO
SMCKBY
Table 76, page 57
and
Table 77, page
Table 87
to
Table
90, and
Table 94
Table
99.
Table 31, page
16.
Virtex-5 Device Pin-to-Pin Output Parameter Guidelines
Table 92
through
Table
97.
Table
99.
6.
Table 27, page
14. Removed I
into I
values.
VTTRXCQ
VTTRXQ
values in
Table 34, page
17.
LLSKEW
values and note 1 in
Table 35, page
XPPMTOL
Table 53, page
, T
, T
IODDO_T
IODDO_IDATAIN
IODDO_ODATAIN
rows in
Table 71
and the F
MAX
Table
75:
PLL in PMCD Mode Switching Characteristics, page
Table 4
and
Table 84
to
Table 98
to match speed grade designations listed in
Table 96
and
Table
97.
www.xilinx.com
14.
.
Table 30, page
16.
17.
in
Table 34, page
17.
GTX
GRX
Table 51, page
26.
84.
2.
Table 55
for production devices.
/T
.
SMDCCK
SMCCKD
Table 78, page
59.
Guidelines: Revised note 1 in
Table 91
51. Revised the typical and maximum values and
Table 54
and
Table
55.
Guidelines: Revised note 1 in
Table 91
of clock is not an applicable limitation.
Table 53, page
29.
Table 58
and added LVPECL_25.
51.
58.
to
Table
97.
in
Table 87
through
in
Table 90
and
Table 92
through
since it is included in
CCINTQ
18.
29.
, and Note 3 to
Table 64, page
44.
rows in
Table
74, revised -2 value for smallest
OUTMAX
56.
in
Table 35,
through
Table
96.
Table
51. Also
in
through
Table
97.
Table
90, and
Table
97. Also
Table 4, page
3.
Table
54.
89