FPGA, VIRTEX-5 LXT, 50K, 665FCBGA

XC5VLX50T-1FFG665C

Manufacturer Part NumberXC5VLX50T-1FFG665C
DescriptionFPGA, VIRTEX-5 LXT, 50K, 665FCBGA
ManufacturerXilinx Inc
SeriesVirtex™-5 LXT
XC5VLX50T-1FFG665C datasheets
Product Change Notification
 


Specifications of XC5VLX50T-1FFG665C

No. Of Logic Blocks7200Family TypeVirtex-5
No. Of Speed Grades1Total Ram Bits2211840
No. Of I/o's360Clock ManagementDCM, PLL
I/o Supply Voltage3.3VOperating Frequency Max550MHz
Number Of Logic Elements/cells46080Number Of Labs/clbs3600
Number Of I /o360Voltage - Supply0.95 V ~ 1.05 V
Mounting TypeSurface MountOperating Temperature0°C ~ 85°C
Package / Case665-BBGA, FCBGACore Supply Voltage Range1V
Rohs CompliantYesLead Free Status / RoHS StatusLead free / RoHS Compliant
For Use WithHW-V5-ML561-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML550-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML521-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5GBE-DK-UNI-G - KIT DEV V5 LXT GIGABIT ETHERNET122-1508 - EVALUATION PLATFORM VIRTEX-5Number Of Gates-
Other names122-1565  
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Input/Output Delay Switching Characteristics
Table 64: Input/Output Delay Switching Characteristics
Symbol
IDELAYCTRL
T
Reset to Ready for IDELAYCTRL
IDELAYCTRLCO_RDY
F
REFCLK frequency
IDELAYCTRL_REF
IDELAYCTRL_REF_PRECISION
REFCLK precision
T
Minimum Reset pulse width
IDELAYCTRL_RPW
IODELAY
T
IODELAY Chain Delay Resolution
IDELAYRESOLUTION
Pattern dependent period jitter in delay chain
for clock pattern
T
IDELAYPAT_JIT
Pattern dependent period jitter in delay chain
for random data pattern (PRBS 23)
T
Maximum frequency of CLK input to IODELAY
IODELAY_CLK_MAX
T
/ T
CE pin Setup/Hold with respect to CK
IODCCK_CE
IODCKC_CE
T
/ T
INC pin Setup/Hold with respect to CK
IODCK_INC
IODCKC_INC
T
/ T
RST pin Setup/Hold with respect to CK
IODCK_RST
IODCKC_RST
T
TSCONTROL delay to MUXE/MUXF switching
IODDO_T
and through IODELAY
T
Propagation delay through IODELAY
IODDO_IDATAIN
T
Propagation delay through IODELAY
IODDO_ODATAIN
Notes:
1.
Average Tap Delay at 200 MHz = 78 ps.
2.
Units in ps, peak-to-peak per tap, in High Performance mode.
3.
Delay depends on IODELAY tap setting. See
CLB Switching Characteristics
Table 65: CLB Switching Characteristics
Symbol
Combinatorial Delays
T
An – Dn LUT address to A
ILO
An – Dn LUT address to AMUX/CMUX
An – Dn LUT address to BMUX_A
T
An – Dn inputs to A – D Q outputs
ITO
T
AX inputs to AMUX output
AXA
T
AX inputs to BMUX output
AXB
T
AX inputs to CMUX output
AXC
T
AX inputs to DMUX output
AXD
T
BX inputs to BMUX output
BXB
T
BX inputs to DMUX output
BXD
DS202 (v5.3) May 5, 2010
Product Specification
Virtex-5 FPGA Data Sheet: DC and Switching Characteristics
Description
200.00
Note 3
Note 3
Note 3
TRACE
report for actual values.
Description
www.xilinx.com
Speed Grade
-3
-2
-1
3.00
3.00
3.00
200.00
200.00
±10
±10
±10
50.00
50.00
50.00
6
(1)
1/(64 x F
x 1e
)
REF
0
0
0
±5
±5
±5
300
250
250
0.29
0.34
0.42
–0.06
–0.06
–0.06
0.18
0.20
0.24
0.02
0.04
0.06
0.25
0.28
0.33
–0.12
–0.12
–0.12
Note 3
Note 3
Note 3
Note 3
Note 3
Note 3
Speed Grade
-3
-2
-1
0.08
0.09
0.10
ns, Max
0.20
0.22
0.25
ns, Max
0.31
0.35
0.40
ns, Max
0.67
0.77
0.90
ns, Max
0.39
0.44
0.53
ns, Max
0.46
0.52
0.61
ns, Max
0.31
0.36
0.42
ns, Max
0.55
0.62
0.73
ns, Max
0.36
0.41
0.48
ns, Max
0.45
0.51
0.59
ns, Max
Units
µs
MHz
MHz
ns
ps
Note 2
Note 2
MHz
ns
ns
ns
Units
44