FPGA, VIRTEX-5 LXT, 50K, 665FCBGA

XC5VLX50T-1FFG665C

Manufacturer Part NumberXC5VLX50T-1FFG665C
DescriptionFPGA, VIRTEX-5 LXT, 50K, 665FCBGA
ManufacturerXilinx Inc
SeriesVirtex™-5 LXT
XC5VLX50T-1FFG665C datasheets
Product Change Notification
 


Specifications of XC5VLX50T-1FFG665C

No. Of Logic Blocks7200Family TypeVirtex-5
No. Of Speed Grades1Total Ram Bits2211840
No. Of I/o's360Clock ManagementDCM, PLL
I/o Supply Voltage3.3VOperating Frequency Max550MHz
Number Of Logic Elements/cells46080Number Of Labs/clbs3600
Number Of I /o360Voltage - Supply0.95 V ~ 1.05 V
Mounting TypeSurface MountOperating Temperature0°C ~ 85°C
Package / Case665-BBGA, FCBGACore Supply Voltage Range1V
Rohs CompliantYesLead Free Status / RoHS StatusLead free / RoHS Compliant
For Use WithHW-V5-ML561-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML550-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML521-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5GBE-DK-UNI-G - KIT DEV V5 LXT GIGABIT ETHERNET122-1508 - EVALUATION PLATFORM VIRTEX-5Number Of Gates-
Other names122-1565  
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Table 78: Input Clock Tolerances
Symbol
Duty Cycle Input Tolerance (in %)
T
DUTYCYCRANGE_1
T
DUTYCYCRANGE_1_50
T
DUTYCYCRANGE_50_100
T
DUTYCYCRANGE_100_200
T
DUTYCYCRANGE_200_400
T
DUTYCYCRANGE_400
Input Clock Cycle-Cycle Jitter (Low Frequency Mode)
T
CYCLFDLL
T
CYCLFFX
Input Clock Cycle-Cycle Jitter (High Frequency Mode)
T
CYCHFDLL
T
CYCHFFX
Input Clock Period Jitter (Low Frequency Mode)
T
PERLFDLL
T
PERLFFX
Input Clock Period Jitter (High Frequency Mode)
T
PERHFDLL
T
PERHFFX
Feedback Clock Path Delay Variation
T
CLKFB_DELAY_VAR
Notes:
1.
DLL Outputs are used in these instances to describe the outputs: CLK0, CLK90, CLK180, CLK270, CLK2X, CLK2X180, and CLKDV.
2.
DFS Outputs are used in these instances to describe the outputs: CLKFX and CLKFX180.
3.
If both DLL and DFS outputs are used, follow the more restrictive specifications.
4.
This duty cycle specification does not apply to the GTP_DUAL to DCM or GTX_DUAL to DCM connection. The GTP transceivers drive the
DCMs at the following frequencies: 320 MHz for -1 speed grade devices, 375 MHz for -2 speed grade devices, or 375 MHz for -3 speed
grade devices. The GTX transceivers drive the DCMs at the following frequencies: 450 MHz for -1 speed grade devices or 500 MHz for -2
speed grade devices.
DS202 (v5.3) May 5, 2010
Product Specification
Virtex-5 FPGA Data Sheet: DC and Switching Characteristics
Description
PSCLK only
PSCLK and CLKIN
(1)
CLKIN (using DLL outputs)
300.00
(2)
CLKIN (using DFS outputs)
300.00
(1)
CLKIN (using DLL outputs)
150.00
(2)
CLKIN (using DFS outputs)
150.00
(1)
CLKIN (using DLL outputs)
(2)
CLKIN (using DFS outputs)
(1)
CLKIN (using DLL outputs)
(2)
CLKIN (using DFS outputs)
CLKFB off-chip feedback
www.xilinx.com
Frequency Range
Value
Units
< 1 MHz
25 - 75
1 - 50 MHz
25 - 75
50 - 100 MHz
30 - 70
100 - 200 MHz
40 - 60
(4)
200 - 400 MHz
45 - 55
> 400 MHz
45 - 55
Speed Grade
Units
-3
-2
-1
300.00
345.00
300.00
345.00
150.00
173.00
150.00
173.00
1.00
1.00
1.15
1.00
1.00
1.15
1.00
1.00
1.15
1.00
1.00
1.15
1.00
1.00
1.15
%
%
%
%
%
%
ps
ps
ps
ps
ns
ns
ns
ns
ns
59