XC5VLX50T-1FFG665C Xilinx Inc, XC5VLX50T-1FFG665C Datasheet - Page 59

FPGA, VIRTEX-5 LXT, 50K, 665FCBGA

XC5VLX50T-1FFG665C

Manufacturer Part Number
XC5VLX50T-1FFG665C
Description
FPGA, VIRTEX-5 LXT, 50K, 665FCBGA
Manufacturer
Xilinx Inc
Series
Virtex™-5 LXTr

Specifications of XC5VLX50T-1FFG665C

No. Of Logic Blocks
7200
Family Type
Virtex-5
No. Of Speed Grades
1
Total Ram Bits
2211840
No. Of I/o's
360
Clock Management
DCM, PLL
I/o Supply Voltage
3.3V
Operating Frequency Max
550MHz
Number Of Logic Elements/cells
46080
Number Of Labs/clbs
3600
Number Of I /o
360
Voltage - Supply
0.95 V ~ 1.05 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
665-BBGA, FCBGA
Core Supply Voltage Range
1V
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
HW-V5-ML561-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML550-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML521-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5GBE-DK-UNI-G - KIT DEV V5 LXT GIGABIT ETHERNET122-1508 - EVALUATION PLATFORM VIRTEX-5
Number Of Gates
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Other names
122-1565
Table 78: Input Clock Tolerances
DS202 (v5.3) May 5, 2010
Product Specification
Notes:
1.
2.
3.
4.
Duty Cycle Input Tolerance (in %)
T
T
T
T
T
T
Input Clock Cycle-Cycle Jitter (Low Frequency Mode)
T
T
Input Clock Cycle-Cycle Jitter (High Frequency Mode)
T
T
Input Clock Period Jitter (Low Frequency Mode)
T
T
Input Clock Period Jitter (High Frequency Mode)
T
T
Feedback Clock Path Delay Variation
T
DUTYCYCRANGE_1
DUTYCYCRANGE_1_50
DUTYCYCRANGE_50_100
DUTYCYCRANGE_100_200
DUTYCYCRANGE_200_400
DUTYCYCRANGE_400
CYCLFDLL
CYCLFFX
CYCHFDLL
CYCHFFX
PERLFDLL
PERLFFX
PERHFDLL
PERHFFX
CLKFB_DELAY_VAR
DLL Outputs are used in these instances to describe the outputs: CLK0, CLK90, CLK180, CLK270, CLK2X, CLK2X180, and CLKDV.
DFS Outputs are used in these instances to describe the outputs: CLKFX and CLKFX180.
If both DLL and DFS outputs are used, follow the more restrictive specifications.
This duty cycle specification does not apply to the GTP_DUAL to DCM or GTX_DUAL to DCM connection. The GTP transceivers drive the
DCMs at the following frequencies: 320 MHz for -1 speed grade devices, 375 MHz for -2 speed grade devices, or 375 MHz for -3 speed
grade devices. The GTX transceivers drive the DCMs at the following frequencies: 450 MHz for -1 speed grade devices or 500 MHz for -2
speed grade devices.
Symbol
PSCLK only
PSCLK and CLKIN
CLKIN (using DLL outputs)
CLKIN (using DFS outputs)
CLKIN (using DLL outputs)
CLKIN (using DFS outputs)
CLKIN (using DLL outputs)
CLKIN (using DFS outputs)
CLKIN (using DLL outputs)
CLKIN (using DFS outputs)
CLKFB off-chip feedback
www.xilinx.com
Description
Virtex-5 FPGA Data Sheet: DC and Switching Characteristics
(1)
(1)
(1)
(1)
(2)
(2)
(2)
(2)
300.00
300.00
150.00
150.00
Frequency Range
1.00
1.00
1.00
1.00
1.00
200 - 400 MHz
-3
100 - 200 MHz
50 - 100 MHz
1 - 50 MHz
> 400 MHz
< 1 MHz
Speed Grade
300.00
300.00
150.00
150.00
1.00
1.00
1.00
1.00
1.00
-2
(4)
25 - 75
25 - 75
30 - 70
40 - 60
45 - 55
45 - 55
345.00
345.00
173.00
173.00
Value
1.15
1.15
1.15
1.15
1.15
-1
Units
Units
ps
ps
ps
ps
ns
ns
ns
ns
ns
%
%
%
%
%
%
59

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