FPGA, VIRTEX-5 LXT, 50K, 665FCBGA

XC5VLX50T-1FFG665C

Manufacturer Part NumberXC5VLX50T-1FFG665C
DescriptionFPGA, VIRTEX-5 LXT, 50K, 665FCBGA
ManufacturerXilinx Inc
SeriesVirtex™-5 LXT
XC5VLX50T-1FFG665C datasheets
Product Change Notification
 


Specifications of XC5VLX50T-1FFG665C

No. Of Logic Blocks7200Family TypeVirtex-5
No. Of Speed Grades1Total Ram Bits2211840
No. Of I/o's360Clock ManagementDCM, PLL
I/o Supply Voltage3.3VOperating Frequency Max550MHz
Number Of Logic Elements/cells46080Number Of Labs/clbs3600
Number Of I /o360Voltage - Supply0.95 V ~ 1.05 V
Mounting TypeSurface MountOperating Temperature0°C ~ 85°C
Package / Case665-BBGA, FCBGACore Supply Voltage Range1V
Rohs CompliantYesLead Free Status / RoHS StatusLead free / RoHS Compliant
For Use WithHW-V5-ML561-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML550-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML521-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5GBE-DK-UNI-G - KIT DEV V5 LXT GIGABIT ETHERNET122-1508 - EVALUATION PLATFORM VIRTEX-5Number Of Gates-
Other names122-1565  
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Virtex-5 FPGA
User Guide
UG190 (v5.3) May 17, 2010

XC5VLX50T-1FFG665C Summary of contents

  • Page 1

    Virtex-5 FPGA User Guide UG190 (v5.3) May 17, 2010 ...

  • Page 2

    Xilinx is disclosing this user guide, manual, release note, and/or specification (the "Documentation") to you solely for use in the development of designs to operate with Xilinx hardware devices. You may not reproduce, distribute, republish, download, display, post, or transmit ...

  • Page 3

    Date Version 9/06/06 2.0 Added the LXT platform devices throughout document. Chapter 1: Revised Chapter 2: Updated Chapter 4: Clarified the rules regarding FULL and EMPTY flags on Chapter 5: Revised Chapter 6: and settings. Replaced the link to the ...

  • Page 4

    Date Version 09/11/07 3.1 Chapter 1: Added Revised Chapter 2: Revised DCM reset and locking process in Updated DO[2] description in page Clocks, page Added more steps to values on Figure 2-20, page Chapter 3: Updated to Phase Shift, page ...

  • Page 5

    Date Version 12/11/07 3.2 Chapter 1: Revised description in XC5VLX20T, XC5VLX155, and XC5VLX155T devices to Chapter 2: Added the XC5VLX20T, XC5VLX155, and XC5VLX155T devices to Chapter 3: Revised descriptions of CLKFBOUT and DEN in CLKOUT[0:5]_PHASE and CLKFBOUT_MULT description in Revised ...

  • Page 6

    Date Version 05/09/08 4.2 Revised clock routing resources in Removed example Figure 2-10 on Corrected note 1 in Added Clarified Note Banks 1 and 2. 09/23/08 4.3 Added the TXT platform to Chapter 2: Revised (Default), page ...

  • Page 7

    Date Version 05/01/09 4.7 Chapter 3: Added 7 as one of the values the last sentence of the first paragraph of Determine the Input Frequency, page Chapter 4: In the second paragraph of paragraph. Changed “Clock Cycle ...

  • Page 8

    Virtex-5 FPGA User Guide www.xilinx.com UG190 (v5.3) May 17, 2010 ...

  • Page 9

    Table of Contents Revision History Preface: About This Guide Additional Documentation Additional Support Resources Typographical Conventions Online Document . . . . . . . . . . . . . . . . . . . . . . ...

  • Page 10

    Dynamic Reconfiguration Clock Input - DCLK DCM Control and Data Input Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

  • Page 11

    Interaction of PSEN, PSINCDEC, PSCLK, and PSDONE Phase-Shift Overflow Phase-Shift Characteristics Dynamic Reconfiguration . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

  • Page 12

    PLL Use Models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

  • Page 13

    Output Latches Initialization - INIT (INIT_A or INIT_B 129 Output Latches/Registers Synchronous Set/Reset (SRVAL_[A|B ...

  • Page 14

    FIFO Timing Models and Parameters FIFO Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

  • Page 15

    Distributed RAM Timing Parameters Distributed RAM Timing Characteristics Slice SRL Timing Model and Parameters (Available in SLICEM only 207 Slice SRL Timing Parameters Slice SRL Timing Characteristics Slice Carry-Chain ...

  • Page 16

    Output Slew Rate Attributes Output Drive Strength Attributes PULLUP/PULLDOWN/KEEPER for IBUF, OBUFT, and IOBUF Differential Termination Attribute Virtex-5 FPGA I/O Resource VHDL/Verilog Examples . . . . . . . . . . . . . . . . . ...

  • Page 17

    SSTL2 Class II (2.5V ...

  • Page 18

    IODELAY Primitive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

  • Page 19

    Timing Characteristics Reset Input Timing ISERDES VHDL and Verilog Instantiation Template 365 BITSLIP Submodule . ...

  • Page 20

    Virtex-5 FPGA User Guide UG190 (v5.3) May 17, 2010 ...

  • Page 21

    About This Guide This document describes the Virtex®-5 architecture. Complete and up-to-date documentation of the Virtex-5 family of FPGAs is available on the Xilinx website at http://www.xilinx.com/virtex5. Additional Documentation The following documents are also available for download at http://www.xilinx.com/virtex5. • ...

  • Page 22

    Preface: About This Guide • Virtex-5 FPGA Configuration Guide This all-encompassing configuration guide includes chapters on configuration interfaces (serial and SelectMAP), bitstream encryption, Boundary-Scan and JTAG configuration, reconfiguration techniques, and readback through the SelectMAP and JTAG interfaces. • Virtex-5 FPGA ...

  • Page 23

    Online Document The following conventions are used in this document: Convention Blue text Blue, underlined text Virtex-5 FPGA User Guide UG190 (v5.3) May 17, 2010 Typographical Conventions Meaning or Use See the section Documentation Cross-reference link to a location Refer ...

  • Page 24

    Preface: About This Guide 24 www.xilinx.com Virtex-5 FPGA User Guide UG190 (v5.3) May 17, 2010 ...

  • Page 25

    Clock Resources Global and Regional Clocks For clocking purposes, each Virtex®-5 device is divided into regions. The number of regions varies with device size, eight regions in the smallest device to 24 regions in the largest one. Global I/O and ...

  • Page 26

    Chapter 1: Clock Resources Global Clocking Resources Global clocks are a dedicated network of interconnect specifically designed to reach all clock inputs to the various resources in an FPGA. These networks are designed to have low skew and low duty ...

  • Page 27

    Global Clock Buffers There are 32 global clock buffers in every Virtex-5 device. Each half of the die (top/bottom) contains 16 global clock buffers. A global clock input can directly connect from the P-side of the differential input pin pair ...

  • Page 28

    Chapter 1: Clock Resources Global Clock Buffer Primitives The primitives in Table 1-2: Global Clock Buffer Primitives Primitive BUFGCTRL BUFG BUFGCE BUFGCE_1 BUFGMUX BUFGMUX_1 BUFGMUX_CTRL Notes: 1. All primitives are derived from a software preset of BUFGCTRL. 2. This primitive ...

  • Page 29

    BUFGCTRL is designed to switch between two clock inputs without the possibility of a glitch. When the presently selected clock transitions from High to Low after S0 and S1 change, the output is kept Low until the other (to-be-selected) clock ...

  • Page 30

    Chapter 1: Clock Resources The timing diagram in BUFGCTRL primitives. Exact timing numbers are best found using the speed specification. X-Ref Target - Figure 1 CE0 CE1 S0 S1 IGNORE0 IGNORE1 T BCCKO_O • ...

  • Page 31

    Table 1-4 summarizes the attributes for the BUFGCTRL primitive. Table 1-4: BUFGCTRL Attributes Attribute Name INIT_OUT PRESELECT_I0 PRESELECT_I1 Notes: 1. Both PRESELECT attributes cannot be TRUE at the same time. 2. The LOC constraint is available. BUFG BUFG is simply ...

  • Page 32

    Chapter 1: Clock Resources BUFGCE and BUFGCE_1 Unlike BUFG, BUFGCE is a clock buffer with one clock input, one clock output and a clock enable line. This primitive is based on BUFGCTRL with some pins connected to logic High or ...

  • Page 33

    Figure 1-7 X-Ref Target - Figure 1-7 BUFGCE_1(CE) BUFGCE_1(O) BUFGMUX and BUFGMUX_1 BUFGMUX is a clock buffer with two clock inputs, one clock output, and a select line. This primitive is based on BUFGCTRL with some pins connected to logic ...

  • Page 34

    Chapter 1: Clock Resources X-Ref Target - Figure 1 Figure 1-9: • The current clock is I0. • activated High. • currently High, the multiplexer waits for I0 to ...

  • Page 35

    BUFGMUX_CTRL BUFGMUX_CTRL is a clock buffer with two clock inputs, one clock output, and a select line. This primitive is based on BUFGCTRL with some pins connected to logic High or Low. Figure 1-11 X-Ref Target - Figure 1-11 BUFGMUX_CTRL ...

  • Page 36

    Chapter 1: Clock Resources Additional Use Models Asynchronous Mux Using BUFGCTRL In some cases an application requires immediate switching between clock inputs or bypassing the edge sensitivity of BUFGCTRL. An example is when one of the clock inputs is no ...

  • Page 37

    BUFGMUX_CTRL with a Clock Enable A BUFGMUX_CTRL with a clock enable BUFGCTRL configuration allows the user to choose between the incoming clock inputs. If needed, the clock enable is used to disable the output. shows the timing diagram. X-Ref Target ...

  • Page 38

    Chapter 1: Clock Resources Clock Tree and Nets - GCLK Virtex-5 clock trees are designed for low-skew and low-power operation. Any unused branch is disconnected. The clock trees also manage the load/fanout when all the logic resources are used. All ...

  • Page 39

    ... Table 1-5: Virtex-5 FPGA Clock Regions Device XC5VLX30 XC5VLX50 XC5VLX85 XC5VLX110 XC5VLX155 XC5VLX220 XC5VLX330 XC5VLX20T XC5VLX30T XC5VLX50T XC5VLX85T XC5VLX110T XC5VLX155T XC5VLX220T XC5VLX330T XC5VTX150T XC5VTX240T XC5VSX35T XC5VSX50T XC5VSX95T XC5VSX240T XC5VFX30T XC5VFX70T XC5VFX100T XC5VFX130T XC5VFX200T Virtex-5 FPGA User Guide UG190 (v5.3) May 17, 2010 ...

  • Page 40

    Chapter 1: Clock Resources Regional Clocking Resources Regional clock networks are a set of clock networks independent of the global clock network. Unlike global clocks, the span of a regional clock signal (BUFR) is limited to three clock regions, while ...

  • Page 41

    I/O Clock Buffer - BUFIO The I/O clock buffer (BUFIO clock buffer available in Virtex-5 devices. The BUFIO drives a dedicated clock net within the I/O column, independent of the global clock resources. Thus, BUFIOs are ideally suited ...

  • Page 42

    Chapter 1: Clock Resources X-Ref Target - Figure 1-19 Clock Capable I/O Clock Capable I/O Not all available BUFIOs are shown. Clock Capable I/O Clock Capable I/O Regional Clock Buffer - BUFR The regional clock buffer (BUFR) is another clock ...

  • Page 43

    Each BUFR can drive the four regional clock nets in the region it is located, and the four clock nets in the adjacent clock regions (up to three clock regions). Unlike BUFIOs, BUFRs can drive the ...

  • Page 44

    Chapter 1: Clock Resources BUFR Attributes and Modes Clock division in the BUFR is controlled in software through the BUFR_DIVIDE attribute. Table 1-8 lists the possible values when using the BUFR_DIVIDE attribute. Table 1-8: BUFR_DIVIDE Attribute Attribute Name BUFR_DIVIDE Notes: ...

  • Page 45

    BUFR Use Models BUFRs are ideal for source-synchronous applications requiring clock domain crossing or serial-to-parallel conversion. Unlike BUFIOs, BUFRs are capable of clocking logic resources in the FPGAs other than the IOBs. X-Ref Target - Figure 1-22 I/O Tile I/O ...

  • Page 46

    Chapter 1: Clock Resources Regional Clock Nets In addition to global clock trees and nets, Virtex-5 devices contain regional clock nets. These clock trees are also designed for low-skew and low-power operation. Unused branches are disconnected. The clock trees also ...

  • Page 47

    Clock Management Technology Clock Management Summary The Clock Management Tiles (CMTs) in the Virtex-5 family provide very flexible, high- performance clocking. Each CMT contains two DCMs and one PLL. simplified view of the center column resources including the CMT block, ...

  • Page 48

    ... CMTs, DCMs, and PLLs in each Virtex-5 device. Table 2-1: Available CMT, DCM, and PLL Resources Number of Available Device CMTs XC5VLX20T 1 XC5VLX30 2 XC5VFX30T XC5VLX30T XC5VSX35T XC5VLX50 6 XC5VLX50T XC5VSX50T XC5VFX70T XC5VLX85 XC5VLX85T XC5VSX95T XC5VFX100T XC5VLX110 XC5VLX110T XC5VFX130T XC5VTX150T XC5VLX155 XC5VLX155T XC5VFX200T XC5VLX220 ...

  • Page 49

    Frequency Synthesis Separate outputs provide a doubled frequency (CLK2X and CLK2X180). Another output, CLKDV, provides a frequency that is a specified fraction of the input frequency. Two other outputs, CLKFX and CLKFX180, provide an output frequency derived from the ...

  • Page 50

    Chapter 2: Clock Management Technology DCM Primitives The DCM primitives DCM_BASE and DCM_ADV are shown in X-Ref Target - Figure 2-2 DCM_BASE Primitive The DCM_BASE primitive accesses the basic frequently used DCM features and simplifies the user-interface ports. The clock ...

  • Page 51

    DCM_ADV Primitive The DCM_ADV primitive has access to all DCM features and ports available in DCM_BASE plus additional ports for the dynamic reconfiguration feature superset of the DCM_BASE primitive. DCM_ADV uses all the DCM features including clock ...

  • Page 52

    Chapter 2: Clock Management Technology Feedback Clock Input - CLKFB The feedback clock (CLKFB) input pin provides a reference or feedback signal to the DCM to delay-compensate the clock outputs, and align them with the clock input. To provide the ...

  • Page 53

    Dynamic Reconfiguration Clock Input - DCLK The dynamic reconfiguration clock (DCLK) input pin provides the source clock for the DCM's dynamic reconfiguration circuit. The frequency of DCLK can be asynchronous (in phase and frequency) to CLKIN. The dynamic reconfiguration clock ...

  • Page 54

    Chapter 2: Clock Management Technology Phase-Shift Enable Input - PSEN The phase-shift enable (PSEN) input signal must be synchronous with PSCLK. A variable phase-shift operation is initiated by the PSEN input signal. It must be activated for one period of ...

  • Page 55

    Output Clock, 90° Phase Shift - CLK90 The CLK90 output clock provides a clock with the same frequency as the DCM’s CLK0 phase-shifted by 90°. 1x Output Clock, 180° Phase Shift - CLK180 The CLK180 output clock provides a ...

  • Page 56

    Chapter 2: Clock Management Technology DCM Status and Data Output Ports Locked Output - LOCKED The LOCKED output indicates whether the DCM clock outputs are valid, i.e., the outputs exhibit the proper frequency and phase. After a reset, the DCM ...

  • Page 57

    Table 2-4: DCM Status Mapping to DO Bus (Continued) DO Bit DO[3] DO[15:4] When LOCKED is Low (during reset or the locking process), all the status signals are deasserted Low. Dynamic Reconfiguration Ready Output - DRDY The dynamic reconfiguration ready ...

  • Page 58

    Chapter 2: Clock Management Technology DCM Attributes A handful of DCM attributes govern the DCM functionality. applicable DCM attributes. This section provides a detailed description of each attribute. For more information on applying these attributes in UCF, VHDL, or Verilog ...

  • Page 59

    CLKIN_DIVIDE_BY_2 Attribute The CLKIN_DIVIDE_BY_2 attribute is used to enable a toggle flip-flop in the input clock path to the DCM. When set to FALSE, the effective CLKIN frequency of the DCM equals the source clock frequency driving the CLKIN input. ...

  • Page 60

    Chapter 2: Clock Management Technology DESKEW_ADJUST Attribute The DESKEW_ADJUST attribute affects the amount of delay in the feedback path. The possible values are SYSTEM_SYNCHRONOUS, SOURCE_SYNCHRONOUS ..., or 31. The default value is SYSTEM_SYNCHRONOUS. For most designs, ...

  • Page 61

    FACTORY_JF Attribute The Factory_JF attribute affects the DCMs jitter filter characteristics. This attribute controls the DCM tap update rate. The default value is 0xF0F0 corresponding to DLL_FREQUENCY_MODE = LOW and DLL_FREQUENCY_MODE = HIGH. PHASE_SHIFT Attribute The PHASE_SHIFT attribute determines the ...

  • Page 62

    Chapter 2: Clock Management Technology Table 2-6: DCM Attributes (Continued) DCM Attribute Name CLKOUT_PHASE_SHIFT This attribute specifies the phase- shift mode. DESKEW_ADJUST This affects the amount of delay in the feedback path, and should be used for source-synchronous interfaces. DFS_FREQUENCY_MODE ...

  • Page 63

    DCM Design Guidelines This section provides a detailed description on using the Virtex-5 FPGA DCM and design guidelines. Clock Deskew The Virtex-5 FPGA DCM offers a fully digital, dedicated, on-chip clock deskew. The deskew feature provides zero propagation delay between ...

  • Page 64

    Chapter 2: Clock Management Technology Input Clock Requirements The clock input of the DCM can be driven either by an IBUFG/IBUFGDS, IBUF, BUFGMUX BUFGCTRL. Since there is no dedicated routing between an IBUF and a DCM clock input, ...

  • Page 65

    Output Clocks Any or all of the DCM’s nine clock outputs can be used to drive a global clock network. The fully-buffered global clock distribution network minimizes clock skew caused by loading differences. By monitoring a sample of the output ...

  • Page 66

    Chapter 2: Clock Management Technology X-Ref Target - Figure 2-4 DCM CLK Source IBUFG Feedback Tap Delays System-Synchronous Default Setting Figure 2-4: DCM and Feedback Tap-Delay Elements This delay element allows adjustment of the effective clock delay between the clock ...

  • Page 67

    Downstream DCMs when two or more DCMs are cascaded • DCMs with external feedback • DCMs with an external CLKIN that does not come from a dedicated clock input pin. Source-Synchronous Setting When DESKEW_ADJUST is set to source-synchronous mode, ...

  • Page 68

    Chapter 2: Clock Management Technology Only when feedback is provided to the CLKFB input of the DCM is the frequency synthesizer output phase aligned to the clock output, CLK0. The internal operation of the frequency synthesizer is complex and beyond ...

  • Page 69

    In the FIXED, VARIABLE_POSITIVE, and VARIABLE_CENTER phase-shift mode, the PHASE_SHIFT attribute is in the numerator of the following equation. Phase Shift (ns) = (PHASE_SHIFT/256) × PERIOD Where PERIOD In VARIABLE_CENTER and FIXED modes, the full range of the PHASE_SHIFT attribute ...

  • Page 70

    Chapter 2: Clock Management Technology • If PERIODCLKIN = FINE_SHIFT_RANGE, then the PHASE_SHIFT in variable- positive mode is limited to +255. In fixed and variable-center mode the PHASE_SHIFT is limited to ±255. If PERIODCLKIN ≤ FINE_SHIFT_RANGE, then the PHASE_SHIFT in ...

  • Page 71

    DCM_TAP. Changing the ratio of V proportional to the size of the DCM_TAP at the specific voltage and temperature. Interaction of PSEN, PSINCDEC, PSCLK, and PSDONE The variable and direct phase-shift modes are controlled by the PSEN, PSINCDEC, PSCLK, and ...

  • Page 72

    Chapter 2: Clock Management Technology Phase-Shift Overflow The phase-shift overflow (DO[0]) status signal is asserted when either of the following conditions is true: • The DCM is phase-shifted beyond the allowed phase-shift value. In this case, the phase-shift overflow signal ...

  • Page 73

    Dynamic Reconfiguration The Dynamic Reconfiguration Ports (DRPs) can update the initial DCM settings without reloading a new bit stream to the FPGA. The DRP address mapping changed in Virtex-5 FPGAs. The Virtex-5 FPGA Configuration Guide provides more information on using ...

  • Page 74

    Chapter 2: Clock Management Technology PLL To and From DCM Figure 2-7 same CMT block. The PLL can drive either DCM in the same CMT block using a dedicated connection. Similarly, the DCM can drive the PLL within the same ...

  • Page 75

    Application Examples The Virtex-5 FPGA DCM can be used in a variety of creative and useful applications. The following examples show some of the more common applications. Standard Usage The circuit in access to RST and LOCKED pins. This example ...

  • Page 76

    Chapter 2: Clock Management Technology X-Ref Target - Figure 2-9 Outside FPGA Inside FPGA IBUFG CLKIN CLKFB IBUFG RST PSINCDEC PSEN PSCLK DADDR[6:0] DI[15:0] DWE DEN DCLK Figure 2-9: Board-Level Clock Using DDR Register with External Feedback X-Ref Target - ...

  • Page 77

    Board Deskew with Internal Deskew Some applications require board deskew with internal deskew to interface with other devices. These applications can be implemented using two or more DCM. The circuit shown in Figure 2-11 devices in the same system. Virtex-5 ...

  • Page 78

    Chapter 2: Clock Management Technology X-Ref Target - Figure 2-11 IBUFG IBUFG IBUFG This circuit can be duplicated to multiple Virtex devices. Use CLKDLL for Virtex and Virtex-E devices, DCM for Virtex-II and Virtex-II Pro devices. Figure 2-11: Board Deskew ...

  • Page 79

    The example in than Virtex FPGAs. X-Ref Target - Figure 2-12 IBUFG IBUFG Figure 2-12: Board Deskew with Internal Deskew Interfacing to Other Components Virtex-5 FPGA User Guide UG190 (v5.3) May 17, 2010 Figure 2-12 shows an interface from Virtex-5 ...

  • Page 80

    Chapter 2: Clock Management Technology Clock Switching Between Two DCMs Figure 2-13 DCMs locked. X-Ref Target - Figure 2-13 IBUFG CLKA IBUFG 80 illustrates switching between two clocks from two DCMs while keeping both DCM_ADV CLKIN CLK0 CLK90 CLK180 CLKFB ...

  • Page 81

    DCM with PLL The PLL can be used to drive the DCM to reduce the source clock’s incoming jitter before inputting DCM. This setup reduces the source clock jitter while enabling user access to all available DCM clock outputs. same ...

  • Page 82

    Chapter 2: Clock Management Technology It is also possible to use the DCM to drive a PLL. This setup reduces the overall jitter of both the source clock and the DCM clock output. In this case, only up to two ...

  • Page 83

    X-Ref Target - Figure 2-16 VHDL and Verilog Templates, and the Clocking Wizard VHDL and Verilog instantiation templates are available in the Libraries Guide for all primitives. In addition, VHDL and Verilog files are generated by the Clocking Wizard in ...

  • Page 84

    Chapter 2: Clock Management Technology DCM Timing Models The following timing diagrams describe the behavior of the DCM clock outputs under four different conditions: 1. Reset/Lock 2. Fixed-Phase Shifting 3. Variable-Phase Shifting 4. Status Flags Reset/Lock In Figure 2-17, the ...

  • Page 85

    Fixed-Phase Shifting In Figure 2-18, the DCM outputs the correct frequency. However, the clock outputs are not in phase with the desired clock phase. The clock outputs are phase-shifted to appear sometime later than the input clock, and the LOCKED ...

  • Page 86

    Chapter 2: Clock Management Technology Variable-Phase Shifting In Figure 2-19, the CLK0 output is phase-shifted using the dynamic phase-shift adjustments in the synchronous user interface. The PSDONE signal is asserted for one cycle when the DCM completes one phase adjustment. ...

  • Page 87

    Status Flags The example in shift overflow and CLKIN/CLKFB/CLKFX failure. X-Ref Target - Figure 2-20 CLKIN CLKFB CLKFX DO(0) DO(1) DO(2) 1 PSCLK PSEN PSDONE DO(3) • Clock Event 1 Prior to the beginning of this timing diagram, CLK0 (not ...

  • Page 88

    Chapter 2: Clock Management Technology Legacy Support The Virtex-5 FPGA DCMs (DCM_BASE and DCM_ADV) have exactly the same port names as the Virtex-4 FPGA DCMs. However, the DRP address mapping has changed. Refer to the Virtex-5 FPGA Configuration Guide for ...

  • Page 89

    Phase-Locked Loops (PLLs) Introduction The clock management tile (CMT) in Virtex-5 FPGAs includes two DCMs and one PLL. There are dedicated routes within a CMT to couple together various components. Each block within the tile can be treated separately, however, ...

  • Page 90

    Chapter 3: Phase-Locked Loops (PLLs) X-Ref Target - Figure 3-1 From any IBUFG implementation From any BUFG implementation Figure 3-1: Block Diagram of the Virtex-5 FPGA CMT Phase Locked Loop (PLL) Virtex-5 devices contain up to six CMT tiles. The ...

  • Page 91

    Input muxes select the reference and feedback clocks from either the IBUFG, BUFG, IBUF, PLL outputs, or one of the DCMs. Each clock input has a programmable counter D. The Phase-Frequency Detector (PFD) compares both phase and frequency of the ...

  • Page 92

    Chapter 3: Phase-Locked Loops (PLLs) General Usage Description PLL Primitives Figure 3-4 X-Ref Target - Figure 3-4 CLKIN1 CLKFBIN RST PLL_BASE Primitive The PLL_BASE primitive provides access to the most frequently used features of a stand alone PLL. Clock deskew, ...

  • Page 93

    PLL_ADV Primitive The PLL_ADV primitive provides access to all PLL_BASE features plus additional ports for clock switching, connectivity to DCMs in the same CMT, and access to the Dynamic Reconfiguration Port (DRP). The ports are listed in can be found ...

  • Page 94

    Chapter 3: Phase-Locked Loops (PLLs) PLL outputs are programmed to provide a 533 MHz PowerPC® processor clock, a 266 MHz PowerPC processor gasket clock, a 178 MHz clock, a 133 MHz memory interface clock MHz PCI™ clock, and ...

  • Page 95

    Phase Shift In many cases, there needs phase shift between clocks. The phase shift resolution in time units is defined as 1/8 F shifted clocks at 45° each. The higher the VCO frequency, the smaller ...

  • Page 96

    Chapter 3: Phase-Locked Loops (PLLs) possible output frequencies for the second output frequency. Continue this process until all the output frequencies are selected. The constraints used to determine the allowed M and D values are shown in the following equations: ...

  • Page 97

    Table 3-3: PLL Ports (Continued) Pin Name I/O The dynamic reconfiguration data input (DI) bus provides reconfiguration data. DI[15:0] Input When not used, all bits must be set to zero. The dynamic reconfiguration write enable (DWE) input pin provides the ...

  • Page 98

    Chapter 3: Phase-Locked Loops (PLLs) PLL Attributes Table 3-4: PLL Attributes Attribute Type COMPENSATION String SYSTEM_SYNCHRONOUS SOURCE_SYNCHRONOUS BANDWIDTH String CLKOUT[0:5]_DIVIDE Integer CLKOUT[0:5]_PHASE Real CLKOUT[0:5]_ Real DUTY_CYCLE CLKFBOUT_MULT Integer 98 Allowed Values Default SYSTEM_ SYNCHRONOUS HIGH OPTIMIZED LOW OPTIMIZED 1 to ...

  • Page 99

    Table 3-4: PLL Attributes (Continued) Attribute Type DIVCLK_DIVIDE Integer CLKFBOUT_PHASE Real REF_JITTER Real CLKIN1_PERIOD Real CLKIN2_PERIOD Real CLKOUT[0:5]_ String DESKEW_ADJUST RESET_ON_LOSS String _OF_LOCK Virtex-5 FPGA User Guide UG190 (v5.3) May 17, 2010 Allowed Values Default 0.0 ...

  • Page 100

    Chapter 3: Phase-Locked Loops (PLLs) PLL CLKIN1 and CLKIN2 Usage CLKIN1 is the general purpose input to the PLL. The CLKIN2 pin is used to dynamically switch between CLKIN1 and CLKIN2 during operation, as selected by the CLKINSEL pin. If ...

  • Page 101

    PLLs in the bottom half of the Virtex-5 device are driven by the global clock pins in bank4 and can be paired as listed in Table 3-7: PLLs in the Bottom Half Pairing CLKIN1 IO_L9P_GC_4 IO_L8P_GC_4 IO_L7P_GC_4 IO_L6P_GC_4 IO_L5P_GC_4 Other ...

  • Page 102

    Chapter 3: Phase-Locked Loops (PLLs) Counter Control The PLL output counters provide a wide variety of synthesized clock using a combination of DIVIDE, DUTY_CYCLE, and PHASE. impact the counter output. The top waveform represents either the output from the VCO ...

  • Page 103

    Clock Shifting The PLL output clocks can be shifted by inserting delay by selecting one of the eight phases in either the reference or the feedback path. edge at the output of the PLL without any shifting versus the two ...

  • Page 104

    Chapter 3: Phase-Locked Loops (PLLs) X-Ref Target - Figure 3-8 135° VCO 8 Phases 180° 225° 270° 315° Counter Outputs All “O” counters are equivalent, anything O0 can do, O1 can do. The PLL outputs are flexible when connecting to ...

  • Page 105

    Missing Input Clock or Feedback Clock When the input clock or feedback clock is lost, the PLL will drive the output clocks to a lower or higher frequency, causing all of the output clocks to increase/decrease in frequency. The frequency ...

  • Page 106

    Chapter 3: Phase-Locked Loops (PLLs) PLL with Internal Feedback The PLL feedback can be internal to the PLL when the PLL is used as a synthesizer or jitter filter and there is no required phase relationship between the PLL input ...

  • Page 107

    In some cases precise alignment will not occur because of the difference in loading between the input capacitance of the external component and the feedback path capacitance of the FPGA. For example, the external components can have an input capacitance ...

  • Page 108

    Chapter 3: Phase-Locked Loops (PLLs) PLL Driving DCM A second option for reduce clock jitter is to use the PLL to clean-up the input clock jitter before driving into the DCM. This will improve the output jitter of all DCM ...

  • Page 109

    PLL to PLL Connection The PLL can be cascaded to allow generation of a greater range of clock frequencies. The frequency range restrictions still apply. final output frequency and the input frequency and counter settings of the two PLLs (Figure ...

  • Page 110

    Chapter 3: Phase-Locked Loops (PLLs) PLL Application Example The following PLL attribute settings result in a wide variety of synthesized clocks: CLKOUT0_PHASE = 0; CLKOUT0_DUTY_CYCLE = 0.5; CLKOUT0_DIVIDE = 2; CLKOUT1_PHASE = 90; CLKOUT1_DUTY_CYCLE = 0.5; CLKOUT1_DIVIDE = 2; CLKOUT2_PHASE ...

  • Page 111

    PLL in Virtex-4 FPGA PMCD Legacy Mode Virtex-5 devices do not have Phase-Matched Clock Dividers (PMCDs). The Virtex-5 FPGA PLL supports the Virtex-4 FPGA PMCD mode of operation. To take advantage of the inherently more powerful features of the Virtex-5 ...

  • Page 112

    Chapter 3: Phase-Locked Loops (PLLs) Table 3-8: Mapping of Port Names (Continued) Virtex-4 FPGA Port Name CLKB1 CLKC1 CLKD1 Table 3-9 shows the PLL attributes in Virtex-4 FPGA PMCD legacy mode. Table 3-9: PLL Attributes When in Virtex-4 FPGA PMCD ...

  • Page 113

    Block RAM Block RAM Summary The block RAM in Virtex-5 FPGAs stores up to 36K bits of data and can be configured as either two independent 18 Kb RAMs, or one 36 Kb RAM. Each 36 Kb block RAM can ...

  • Page 114

    Chapter 4: Block RAM • All inputs are registered with the port clock and have a setup-to-clock timing specification. • All outputs have a read function or a read-during-write function, depending on the state of the write enable (WE) pin. ...

  • Page 115

    Table 4-1: Parity Use Sceneries (Continued) Primitive RAMB36 RAMB36 RAMB36 RAMB36 Notes not use parity bits DIP/DOP when one port widths is less than nine and another port width is nine or greater. Block RAM Introduction In addition ...

  • Page 116

    Chapter 4: Block RAM X-Ref Target - Figure 4-1 Table 4-2: True Dual-Port Names and Descriptions Port Name DI[A|B] (1) DIP[A|B] ADDR[A|B] WE[A|B] EN[A|B] SSR[A|B] CLK[A|B] DO[A|B] DOP[A|B] REGCE[A|B] CASCADEINLAT[A|B] 116 CASCADEOUTLATA CASCADEOUTLATB CASCADEOUTREGA CASCADEOUTREGB 36-Kbit Block RAM DIA DIPA ...

  • Page 117

    Table 4-2: True Dual-Port Names and Descriptions (Continued) Port Name CASCADEOUTLAT[A|B] CASCADEINREG[A|B] CASCADEOUTREG[A|B] Notes: 1. The Data-In Buses - DI[A|B]<#:0> & DIP[A|B]<#:0> pins. Read Operation In latch mode, the read operation uses one clock edge. The read address is registered ...

  • Page 118

    Chapter 4: Block RAM WRITE_FIRST or Transparent Mode (Default) In WRITE_FIRST mode, the input data is simultaneously written into memory and stored in the data output (transparent write), as shown in correspond to latch mode when the optional output pipeline ...

  • Page 119

    X-Ref Target - Figure 4-4 CLK WE DI ADDR DO EN Conflict Avoidance Virtex-5 FPGA block RAM memory is a true dual-port RAM where both ports can access any memory location at any time. When accessing the same memory location ...

  • Page 120

    Chapter 4: Block RAM Additional Block RAM Features in Virtex-5 Devices Optional Output Registers The optional output registers improve design performance by eliminating routing delay to the CLB flip-flops for pipelined operation. An independent clock and clock enable input is ...

  • Page 121

    Simple Dual-Port Block RAM Each 18 Kb block and 36 Kb block can also be configured in a simple dual-port RAM mode. In this mode, the block RAM port width doubles to 36 bits for the 18 Kb block RAM ...

  • Page 122

    Chapter 4: Block RAM Cascadable Block RAM In the Virtex-5 block RAM architecture, two 32K x 1 RAMs can be combined to form one 64K x 1 RAM without using local interconnect or additional CLB logic resources. Any two adjacent ...

  • Page 123

    Table 4-4: Available Byte-wide Write Enables (Continued) Primitive RAMB18 RAMB18SDP When the RAMB36 is configured for a 36-bit or 18-bit wide data path, any port can restrict writing to specified byte locations within the data word. If configured in READ_FIRST ...

  • Page 124

    Chapter 4: Block RAM Figure 4-9 (RAMB36). X-Ref Target - Figure 4-9 Table 4-5: Virtex-5 FPGA Block RAM, FIFO, Simple Dual Port, and ECC Primitives Primitive RAMB36 RAMB36SDP FIFO36 FIFO36_72 RAMB18 RAMB18SDP FIFO18 FIFO18_36 Notes: 1. All eight primitives are ...

  • Page 125

    Block RAM Port Signals Each block RAM port operates independently of the other while accessing the same set of 36K-bit memory cells. Clock - CLK[A|B] Each port is fully synchronous with independent clock pins. All port input pins have setup ...

  • Page 126

    Chapter 4: Block RAM Table 4-6: Port Aspect Ratio for RAMB18 and RAMB18SDP Port Data Width Port Address Width (RAMB18SDP) 9 Table 4-7: Port Aspect Ratio for RAMB36 Port ...

  • Page 127

    Cascade In - CASCADEINLAT[A|B] and CASCADEINREG[A|B] The CASCADEIN pins are used to connect two block RAMs to form the 64K x 1 mode (Figure 4-10.) This pin is used when the block RAM is the UPPER block RAM, and is ...

  • Page 128

    Chapter 4: Block RAM Block RAM Address Mapping Each port accesses the same set of 18,432 or 36,864 memory cells using an addressing scheme dependent on whether RAMB18 or RAMB36. The physical RAM locations addressed for a ...

  • Page 129

    Table 4-9: Block RAM Initialization Attributes Attribute INIT_00 INIT_01 INIT_02 INIT_0E INIT_0F INIT_10 INIT_1F INIT_20 INIT_2F INIT_30 INIT_3F INIT_7F Content Initialization - INITP_xx INITP_xx attributes define the initial contents of the memory cells corresponding to DIP/DOP buses (parity bits). By ...

  • Page 130

    Chapter 4: Block RAM Output Latches/Registers Synchronous Set/Reset (SRVAL_[A|B]) The SRVAL (single-port) or SRVAL_A and SRVAL_B (dual-port) attributes define output latch values when the SSR input is asserted. The width of the SRVAL (SRVAL_A and SRVAL_B) attribute is the port ...

  • Page 131

    Block RAM Location Constraints Block RAM instances can have LOC properties attached to them to constrain placement. Block RAM placement locations differ from the convention used for naming CLB locations, allowing LOC properties to transfer easily from array to array. ...

  • Page 132

    Chapter 4: Block RAM • When using these attributes, if both write ports or both read ports are set to 0, the Xilinx ISE tools will not implement the design. In simple dual-port mode, the port width is fixed and ...

  • Page 133

    In x72 simple dual-port mode, WE[7:0] is connected to the eight user WE inputs. Additional Block RAM Primitives In addition to RAMB18 and RAMB36, there are other block RAM primitives available for specific implementations. RAMB18SDP and RAMB36SDP implement the ...

  • Page 134

    Chapter 4: Block RAM X-Ref Target - Figure 4-12 CLK RAMEN REGCE SSR DBRAM D0 DO Figure 4-12: SSR Operation in Register Mode with REGCE High X-Ref Target - Figure 4-13 CLK RAMEN REGCE SSR DBRAM D0 SSR only sets/resets ...

  • Page 135

    Block RAM Timing Parameters Table 4-11 shows the Virtex-5 FPGA block RAM timing parameters. Table 4-11: Block RAM Timing Parameters Parameter Function Setup and Hold Relative to Clock (CLK Setup time (before clock edge) and T RxCK_x T ...

  • Page 136

    Chapter 4: Block RAM Block RAM Timing Characteristics The timing diagram in without the optional output register. The timing for read-first and no-change modes are similar. For timing using the optional output register, an additional clock latency appears at the ...

  • Page 137

    Clock Event 2 Write Operation During a write operation, the content of the memory at the location specified by the address on the ADDR inputs is replaced by the value on the DI pins and is immediately reflected on the ...

  • Page 138

    Chapter 4: Block RAM Block RAM Timing Model Figure 4-15 This example takes the simplest paths on and off chip (these paths can vary greatly depending on the design). This timing model demonstrates how and where the block RAM timing ...

  • Page 139

    Block RAM Retargeting Table 4-12 FPGA block RAM design in a new Virtex-5 FPGA design. Table 4-12: Block RAM Retargeting Virtex-4 Block RAM Port Width Primitive Depth R/W RAMB16 RAMB18 True dual port ...

  • Page 140

    Chapter 4: Block RAM Data flow control is automatic; the user need not be concerned about the block RAM addressing sequence, although WRCOUNT and RDCOUNT are also brought out, if needed for special applications. The user must, however, observe the ...

  • Page 141

    Table 4-13: FIFO Capacity Standard Mode 18 Kb FIFO 36 Kb FIFO entries by 4 bits entries by 4 bits entries by 9 bits entries by 9 bits ...

  • Page 142

    Chapter 4: Block RAM FIFO Architecture: a Top-Level View Figure 4-17 write pointer, and status flag logic are dedicated for FIFO use only. X-Ref Target - Figure 4-17 WRCOUNT DIN/DINP WRCLK FIFO Primitives Figure 4-18 X-Ref Target - Figure 4-18 ...

  • Page 143

    Figure 4-19 X-Ref Target - Figure 4-19 FIFO Port Descriptions Table 4-15 Table 4-15: FIFO I/O Port Names and Descriptions Port Name DI DIP WREN WRCLK RDEN RDCLK RESET DO DOP FULL ALMOSTFULL EMPTY Virtex-5 FPGA User Guide UG190 (v5.3) ...

  • Page 144

    Chapter 4: Block RAM Table 4-15: FIFO I/O Port Names and Descriptions (Continued) Port Name ALMOSTEMPTY RDCOUNT WRCOUNT WRERR RDERR FIFO Operations Reset Reset is an asynchronous signal for both multirate and synchronous FIFO. Reset must be asserted for three ...

  • Page 145

    X-Ref Target - Figure 4-20 RDCLK RDEN EMPTY DO (Standard) DO (FWFT) Status Flags Table 4-16 FIFO. Synchronous FIFOs do not have a clock cycle latency when asserting or deasserting flags. Due to the asynchronous nature of the clocks, the ...

  • Page 146

    Chapter 4: Block RAM relationship, it takes several cascaded flip-flops to guarantee that such a move does not cause glitches or metastable problems. The falling edge of EMPTY is thus delayed by several RDCLK periods after the first write into ...

  • Page 147

    FIFO Attributes Table 4-17 configured by setting the DATA_WIDTH attribute. The section has examples for setting the attributes. Table 4-17: FIFO18 and FIFO36 Attributes Attribute Name ALMOST_FULL_OFFSET ALMOST_EMPTY_OFFSET FIRST_WORD_FALL_THROUGH DO_REG DATA_WIDTH (1, 2) LOC EN_SYN Notes FIFO18 is ...

  • Page 148

    Chapter 4: Block RAM FIFO Almost Full/Empty Flag Offset Range The offset ranges for Almost Empty and Almost Full are listed in Table 4-18: FIFO Data Depth Data Width FIFO18 x4 x9 x18 x36 Notes: 1. ALMOST_EMPTY_OFFSET and ALMOST_FULL_OFFSET for ...

  • Page 149

    Similarly, the ALMOST_EMPTY flag can be used to stop reading. However, this would make it impossible to read the very last entries remaining in the FIFO. The user can ignore the Almost Empty signal and continue to read until EMPTY ...

  • Page 150

    Chapter 4: Block RAM Table 4-20: FIFO Timing Parameters (Continued) Parameter Function (3) T Clock to read pointer RCKO_RDCOUNT output (3) T Clock to write pointer RCKO_WRCOUNT output Reset to Out T Reset to almost empty RCO_AEMPTY output T Reset ...

  • Page 151

    Case 1: Writing to an Empty FIFO Prior to the operations performed in X-Ref Target - Figure 4-21 WRCLK WREN DI RDCLK RDEN DO EMPTY AEMPTY Clock Event 1 and Clock Event 3: Write Operation and Deassertion of EMPTY Signal ...

  • Page 152

    Chapter 4: Block RAM Clock Event 2 and Clock Event 4: Write Operation and Deassertion of Almost EMPTY Signal Three read-clock cycles after the fourth data is written into the FIFO, the Almost EMPTY pin is deasserted to signify that ...

  • Page 153

    Clock Event 1: Write Operation and Assertion of Almost FULL Signal During a write operation to an almost full FIFO, the Almost FULL signal is asserted. • At time T inputs of the FIFO. • At time T the WREN ...

  • Page 154

    Chapter 4: Block RAM Case 3: Reading From a Full FIFO Prior to the operations performed in X-Ref Target - Figure 4-23 WRCLK WREN RDCLK RDEN DO FULL AFULL Clock Event 1 and Clock Event 2: Read Operation and Deassertion ...

  • Page 155

    There is minimum time between a rising read-clock and write-clock edge to guarantee that AFULL will be deasserted. If this minimum is not met, the deassertion of AFULL can take an additional write clock cycle. Case 4: Reading From An ...

  • Page 156

    Chapter 4: Block RAM Clock Event 3: Read Operation and Assertion of Read Error Signal The read error signal pin is asserted when there is no data to be read because the FIFO empty state. • Read ...

  • Page 157

    Case 6: Simultaneous Read and Write for Multirate FIFO Simultaneous read and write operations for an asynchronous FIFO is not deterministic when the FIFO is at the condition to assert a status flag. The FIFO logic resolves the situation (either ...

  • Page 158

    Chapter 4: Block RAM Connecting FIFOs in Parallel to Increase Width As shown in design. CLB logic is used to implement the AND/OR gates. All the FIFO AFULL signals must be ORed together to created the output AFULL signal and ...

  • Page 159

    ECC Modes Overview In the standard ECC mode (EN_ECC_READ = TRUE and EN_ECC_WRITE = TRUE), both encoder and decoder are enabled. During write, 64-bit data and 8-bit ECC generated parity are stored in the array. The external parity bits are ...

  • Page 160

    Chapter 4: Block RAM Top-Level View of the Block RAM ECC Architecture Figure 4-28 X-Ref Target - Figure 4-28 WRADDR[8:0] RDADDR[8:0] DIP[7:0] 8 ECCPARITY[7:0] 64 DI[63:0] DO_REG 0 DO[63: DO_REG 0 DBITERR DO_REG 0 ...

  • Page 161

    Block RAM and FIFO ECC Primitive Figure 4-29 FIFO36_72 ECC primitive. The FIFO36_72 only supports standard mode. X-Ref Target - Figure 4-29 X-Ref Target - Figure 4-30 Virtex-5 FPGA User Guide UG190 (v5.3) May 17, 2010 shows the block RAM ...

  • Page 162

    Chapter 4: Block RAM Block RAM and FIFO ECC Port Descriptions Table 4-21 Table 4-21: Block RAM ECC Port Names and Descriptions Port Name Direction DI[63:0] Input Data input bus. DIP[7:0] Input Data input parity bus. Used in decode-only mode ...

  • Page 163

    Table 4-22 Table 4-22: FIFO ECC Port Names and Descriptions Port Name Direction DI[63:0] Input Data input bus. DIP[7:0] Input Data input parity bus. Not used when standard mode is used. WREN Input Write enable. When WREN = 1, data ...

  • Page 164

    Chapter 4: Block RAM Block RAM and FIFO ECC Attributes In addition to the built-in registers in the decode and correct logic, the RAMB36SDP primitive allows the use of optional pipeline registers controlled by the DO_REG attribute to produce higher ...

  • Page 165

    ECC Modes of Operation There are three types of ECC operation: standard, encode only, and decode only. The standard ECC mode uses both the encoder and decoder. The various modes of ECC operation in both block RAM and FIFO are ...

  • Page 166

    Chapter 4: Block RAM Standard ECC Set by Attributes EN_ECC_READ = TRUE EN_ECC_WRITE = TRUE Standard ECC Write At time T1W, DI[63: written into memory location a. The corresponding 8 bits of ECC parity PA (hex) are ...

  • Page 167

    Similarly, at time T2W and T3W, DI[63: and C, together with their corresponding parity bits PB (hex) and PC (hex) are written into memory locations b and c. PB and PC appear at output ECCPARITY[7:0] shortly after T2W ...

  • Page 168

    Chapter 4: Block RAM ECC Timing Characteristics The various ECC timing parameters are also shown in Since write clock and read clock are independent of each other, all write timing in Figure 4-31 RDCLK. Standard ECC Write Timing • At ...

  • Page 169

    Encode-Only ECC Write Timing • Setup/hold time for WREN and WRADDR are the same as standard ECC. • At time TRDCK_DI_ECC (encode-only ECC), before time T1W, write data A (hex) becomes valid at the DI[63:0] inputs of the block RAM. ...

  • Page 170

    Chapter 4: Block RAM Table 4-25: Block RAM ECC Mode Timing Parameters (Continued) Parameter Function Clock to ECC Delays T Clock to ECC RCKO_ECC_PARITY Parity Output (3) (encode-only mode) (3) T Clock to ECC RCKO_ECC_SBITERR Single-Bit-Error Output (4) T Clock ...

  • Page 171

    Block RAM ECC VHDL and Verilog Templates VHDL and Verilog templates are available in the Libraries Guide. Legal Block RAM and FIFO Combinations The block RAM–FIFO combinations shown in RAMB36 primitive. When placing block RAM and FIFO primitives in the ...

  • Page 172

    Chapter 4: Block RAM 172 www.xilinx.com Virtex-5 FPGA User Guide UG190 (v5.3) May 17, 2010 ...

  • Page 173

    Configurable Logic Blocks (CLBs) CLB Overview The Configurable Logic Blocks (CLBs) are the main logic resources for implementing sequential as well as combinatorial circuits. Each CLB element is connected to a switch matrix for access to the general routing matrix ...

  • Page 174

    Chapter 5: Configurable Logic Blocks (CLBs) X-Ref Target - Figure 5-2 Figure 5-2: Row and Column Relationship between CLBs and Slices Slice Description Every slice contains four logic-function generators (or look-up tables), four storage elements, wide-function multiplexers, and carry logic. ...

  • Page 175

    X-Ref Target - Figure 5-3 DI DI2 D6 A6 DPRAM64/ SPRAM64/32 SRL32 SRL16 LUT D2 A2 DI1 RAM ROM D1 A1 MC31 WA1-WA6 WA7 WA8 DX CI DI2 C6 A6 DPRAM64/32 C5 ...

  • Page 176

    Chapter 5: Configurable Logic Blocks (CLBs) X-Ref Target - Figure 5 LUT D5 A5 ROM LUT C5 A5 ROM ...

  • Page 177

    ... Table 5-2: Virtex-5 FPGA Logic Resources Available in All CLBs CLB Array Device Row x Column XC5VLX20T XC5VLX30 XC5VFX30T XC5VLX30T XC5VSX35T XC5VLX50 120 x 30 XC5VLX50T 120 x 30 XC5VSX50T 120 x 34 XC5VFX70T 160 x 38 XC5VLX85 120 x 54 XC5VLX85T 120 x 54 XC5VSX95T 160 x 46 XC5VFX100T 160 x 56 XC5VLX110 160 x 54 ...

  • Page 178

    Chapter 5: Configurable Logic Blocks (CLBs) Look-Up Table (LUT) The function generators in Virtex-5 FPGAs are implemented as six-input look-up tables (LUTs). There are six independent inputs (A inputs - A1 to A6) and two independent outputs (O5 and O6) ...

  • Page 179

    Table 5-3: Truth Table when SRLOW is Used (Default Condition) (Continued) Table 5-4: Truth Table when SRHIGH is Used X-Ref Target - Figure 5-5 SRHIGH and SRLOW can be set individually for each storage element in a slice. The choice ...

  • Page 180

    Chapter 5: Configurable Logic Blocks (CLBs) The initial state after configuration or global initial state is defined by separate INIT0 and INIT1 attributes. By default, setting the SRLOW attribute sets INIT0, and setting the SRHIGH attribute sets INIT1. Virtex-5 devices ...

  • Page 181

    Table 5-5 shows the number of LUTs (four per slice) occupied by each distributed RAM configuration. Table 5-5: Distributed RAM Configuration Notes single-port configuration dual-port configuration quad-port configuration; SDP = simple dual-port configuration. ...

  • Page 182

    Chapter 5: Configurable Logic Blocks (CLBs) X-Ref Target - Figure 5-6 ADDRD[4:0] ADDRC[4:0] ADDRB[4:0] ADDRA[4:0] 182 RAM 32X2Q (DX) DID[1] DI1 (AI/BI/CI/DI) DID[0] DI2 D[5:1] 5 A[6:1] 5 WA[6:1] (CLK) WCLK CLK (WE) WE WED DI1 DI2 C[5:1] 5 A[6:1] ...

  • Page 183

    X-Ref Target - Figure 5-7 WADDR[ RADDR[ Virtex-5 FPGA User Guide UG190 (v5.3) May 17, 2010 RAM 32X6SDP unused unused D[5:1] 5 WADDR[5:1] 5 (CLK) WCLK (WE) WED DATA[1] DATA[2] C[5:1] 5 RADDR[5:1] 5 DATA[3] DATA[4] ...

  • Page 184

    Chapter 5: Configurable Logic Blocks (CLBs) X-Ref Target - Figure 5-8 If four single-port 64 x 1-bit modules are built, the four RAM64X1S primitives can occupy a SLICEM, as long as they share the same clock, write enable, and shared ...

  • Page 185

    X-Ref Target - Figure 5-10 DID ADDRD WCLK WE ADDRC ADDRB ADDRA Virtex-5 FPGA User Guide UG190 (v5.3) May 17, 2010 RAM64X1Q DPRAM64 (DX) DOD O6 DI1 (D[6:1]) A[6:1] WA[6:1] (CLK) CLK (WE) WE DPRAM64 DOC DI1 O6 (C[6:1]) A[6:1] ...

  • Page 186

    Chapter 5: Configurable Logic Blocks (CLBs) X-Ref Target - Figure 5-11 WADDR[6:1] RADDR[6:1] Implementation of distributed RAM configurations with depth greater than 64 requires the usage of wide-function multiplexers (F7AMUX, F7BMUX, and F8MUX). 186 RAM 64X3SDP unused DI1 unused DI2 ...

  • Page 187

    X-Ref Target - Figure 5-12 D A[6:0] WCLK WE If two single-port 128 x 1-bit modules are built, the two RAM128X1S primitives can occupy a SLICEM, as long as they share the same clock, write enable, and shared read and ...

  • Page 188

    Chapter 5: Configurable Logic Blocks (CLBs) X-Ref Target - Figure 5-13 D A[6:0] WCLK WE DPRA[6:0] 188 RAM128X1D A6 (CX) DPRAM64 DX O6 DI1 6 A[6:1] 7 WA[7:1] (CLK) CLK (WE) WE DPRAM64 O6 DI1 6 A[6:1] 7 WA[7:1] CLK ...

  • Page 189

    X-Ref Target - Figure 5-14 D A[7:0] WCLK WE Distributed RAM configurations greater than the provided examples require more than one SLICEM. There are no direct connections between slices to form larger distributed RAM configurations within a CLB or between ...

  • Page 190

    Chapter 5: Configurable Logic Blocks (CLBs) Distributed RAM Data Flow Synchronous Write Operation The synchronous write operation is a single clock-edge operation with an active-High write-enable (WE) feature. When WE is High, the input (D) is loaded into the memory ...

  • Page 191

    In this case, the clock-to-out of the flip-flop determines the overall delay and improves performance. However, one additional cycle of clock latency is added. Any of the 32 bits can be ...

  • Page 192

    Chapter 5: Configurable Logic Blocks (CLBs) Figure 5-17 single LUT. X-Ref Target - Figure 5-17 As mentioned earlier, an additional output (MC31) and a dedicated connection between shift registers allows connecting the last bit of one shift register to the ...

  • Page 193

    X-Ref Target - Figure 5-19 SHIFTIN (D) 5 A[6:0] (CLK) CLK (WE/CE Figure 5-19: 96-bit Shift Register Configuration Virtex-5 FPGA User Guide UG190 (v5.3) May 17, 2010 CX (A5) SRL32 O6 DI1 A[6:2] F7BMUX MC31 CLK WE ...

  • Page 194

    Chapter 5: Configurable Logic Blocks (CLBs) X-Ref Target - Figure 5-20 SHIFTIN (D) A[6:0] CLK possible to create shift registers longer than 128 bits across more than one SLICEM. However, there are no direct connections between slices ...

  • Page 195

    LUT. This operation is asynchronous and independent of the clock and clock-enable signals. Static Read Operation If the 5-bit address is fixed, the Q output always uses the same bit position. This mode implements any shift-register ...

  • Page 196

    Chapter 5: Configurable Logic Blocks (CLBs) Designing Large Multiplexers 4:1 Multiplexer Each LUT can be configured into a 4:1 MUX. The 4:1 MUX can be implemented with a flip- flop in the same slice four 4:1 MUXes can ...

  • Page 197

    Multiplexer Each slice has an F7AMUX and an F7BMUX. These two muxes combine the output of two LUTs to form a combinatorial function inputs (or an 8:1 MUX two 8:1 MUXes can be implemented ...

  • Page 198

    Chapter 5: Configurable Logic Blocks (CLBs) 16:1 Multiplexer Each slice has an F8MUX. F8MUX combines the outputs of F7AMUX and F7BMUX to form a combinatorial function inputs (or a 16:1 MUX). Only one 16:1 MUX can be ...

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    Figure 5-24 X-Ref Target - Figure 5-24 O6 From LUTD O5 From LUTD O6 From LUTC O5 From LUTC O6 From LUTB O5 From ...

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    Chapter 5: Configurable Logic Blocks (CLBs) to create an adder/accumulator. CYINIT is the CIN of the first bit in a carry chain. The CYINIT value can be 0 (for add), 1 (for subtract input (for the dynamic first ...