XC5VLX50T-1FFG665C Xilinx Inc, XC5VLX50T-1FFG665C Datasheet - Page 228

• Manufacturer Part Number: XC5VLX50T-1FFG665C
• Description: FPGA, VIRTEX-5 LXT, 50K, 665FCBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-5 LXTr

Specifications of XC5VLX50T-1FFG665C

• No. Of Logic Blocks: 7200
• Family Type: Virtex-5
• No. Of Speed Grades: 1
• Total Ram Bits: 2211840
• No. Of I/o's: 360
• Clock Management: DCM, PLL
• I/o Supply Voltage: 3.3V
• Operating Frequency Max: 550MHz
• Number Of Logic Elements/cells: 46080
• Number Of Labs/clbs: 3600
• Number Of I /o: 360
• Voltage - Supply: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 665-BBGA, FCBGA
• Core Supply Voltage Range: 1V
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: HW-V5-ML561-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML550-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML521-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5GBE-DK-UNI-G - KIT DEV V5 LXT GIGABIT ETHERNET122-1508 - EVALUATION PLATFORM VIRTEX-5
• Number Of Gates: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 122-1565

Chapter 6: SelectIO Resources
228
Driver with Termination to V
Figure 6-13
X-Ref Target - Figure 6-13
Some I/O standards, such as HSTL Class II, require an output termination to V
Figure
X-Ref Target - Figure 6-14
DCI can provide output termination to V
the impedance of the termination, but not the driver. Both HSTL and SSTL standards need
50 Ω external reference resistors. The DCI output standards supporting drivers with split
termination are shown in
Table 6-2: DCI Output Standards Supporting Split Termination
HSTL_II_DCI
HSTL_II_DCI_18
Figure 6-13: Driver with Termination to V
6-14).
illustrates a driver with single termination inside a Virtex-5 device.
Figure 6-14: Driver with Termination to V
DIFF_HSTL_II_DCI
DIFF_HSTL_II_DCI_18
Virtex-5 FPGA
www.xilinx.com
Table
CCO
6-2.
/2 (Split Termination)
IOB
V
Virtex-5 DCI
CCO
CCO
R
V
CCO
/2 using split termination. DCI only controls
IOB
R
SSTL2_II_DCI
SSTL18_II_DCI
/2
CCO
Using DCI Single Termination
UG190_c6_12_022609
UG190_6_11_021206
Z
Z
0
0
CCO
/2 without DCI
Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010
DIFF_SSTL2_II_DCI
DIFF_SSTL18_II_DCI
CCO
/2 (see