XC5VLX50T-1FFG665C Xilinx Inc, XC5VLX50T-1FFG665C Datasheet - Page 362

FPGA, VIRTEX-5 LXT, 50K, 665FCBGA

XC5VLX50T-1FFG665C

Manufacturer Part Number
XC5VLX50T-1FFG665C
Description
FPGA, VIRTEX-5 LXT, 50K, 665FCBGA
Manufacturer
Xilinx Inc
Series
Virtex™-5 LXTr

Specifications of XC5VLX50T-1FFG665C

No. Of Logic Blocks
7200
Family Type
Virtex-5
No. Of Speed Grades
1
Total Ram Bits
2211840
No. Of I/o's
360
Clock Management
DCM, PLL
I/o Supply Voltage
3.3V
Operating Frequency Max
550MHz
Number Of Logic Elements/cells
46080
Number Of Labs/clbs
3600
Number Of I /o
360
Voltage - Supply
0.95 V ~ 1.05 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
665-BBGA, FCBGA
Core Supply Voltage Range
1V
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
HW-V5-ML561-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML550-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML521-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5GBE-DK-UNI-G - KIT DEV V5 LXT GIGABIT ETHERNET122-1508 - EVALUATION PLATFORM VIRTEX-5
Number Of Gates
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Other names
122-1565

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Chapter 8: Advanced SelectIO Logic Resources
362
Guidelines for Expanding the Serial-to-Parallel Converter Bit Width
X-Ref Target - Figure 8-7
1.
2.
3.
4.
5.
Both ISERDES modules must be adjacent master and slave pairs. Both ISERDES
modules must be in NETWORKING mode because width expansion is not available in
MEMORY mode.
Set the SERDES_MODE attribute for the master ISERDES to MASTER and the slave
ISERDES to SLAVE. See
The user must connect the SHIFTIN ports of the SLAVE to the SHIFTOUT ports of the
MASTER.
The SLAVE only uses the ports Q3 to Q6 as an input.
DATA_WIDTH applies to both MASTER and SLAVE in
Data Input
Figure 8-7: Block Diagram of ISERDES Width Expansion
SERDES_MODE=MASTER
D
D
SERDES_MODE=SLAVE
SHIFTOUT1 SHIFTOUT2
www.xilinx.com
SHIFTIN1
SERDES_MODE
ISERDES
ISERDES
(Master)
(Slave)
SHIFTIN2
Attribute.
Q1
Q2
Q3
Q4
Q5
Q6
Q1
Q2
Q3
Q4
Q5
Q6
Figure
Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010
Data_internal [0:5]
Data_internal [6:9]
8-7.
ug190_8_07_100307

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