XC5VLX50T-1FFG665C Xilinx Inc, XC5VLX50T-1FFG665C Datasheet - Page 384

• Manufacturer Part Number: XC5VLX50T-1FFG665C
• Description: FPGA, VIRTEX-5 LXT, 50K, 665FCBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-5 LXTr

Specifications of XC5VLX50T-1FFG665C

• No. Of Logic Blocks: 7200
• Family Type: Virtex-5
• No. Of Speed Grades: 1
• Total Ram Bits: 2211840
• No. Of I/o's: 360
• Clock Management: DCM, PLL
• I/o Supply Voltage: 3.3V
• Operating Frequency Max: 550MHz
• Number Of Logic Elements/cells: 46080
• Number Of Labs/clbs: 3600
• Number Of I /o: 360
• Voltage - Supply: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 665-BBGA, FCBGA
• Core Supply Voltage Range: 1V
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: HW-V5-ML561-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML550-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML521-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5GBE-DK-UNI-G - KIT DEV V5 LXT GIGABIT ETHERNET122-1508 - EVALUATION PLATFORM VIRTEX-5
• Number Of Gates: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 122-1565

HyperTransport
I
I/O standards
I/O tile
IBUF
IBUFDS
IBUFDS_DIFF_OUT
IBUFG
IBUFGDS
IDDR
IDELAY
IDELAYCTRL
384
class II (1.8V)
class III
class III (1.8V)
class IV
class IV (1.8V)
CSE differential HSTL class II
Differential HSTL class II
differential HSTL class II
HT
bank rules
compatibility
differential I/O
single-ended I/O
ILOGIC
IOB
OLOGIC
PULLUP/PULLDOWN/KEEPER
OPPOSITE_EDGE mode
ports
primitive
SAME_EDGE mode
SAME_EDGE_PIPELINED mode
defined
attributes
delay mode
IDELAYCTRL
increment/decrement
primitive
switching characteristics
timing
instantiating
location
233
319
237
320
26
217
296
234
fixed
variable
zero-hold time
RDY port
325
217
,
26
321
233
325
330
,
259
260
217
339
234
217
321
326
218
329
337
325
298
340
325
265
299
270
271
341
337
235
218
,
218
342
325
320
328
330
319
256
264
,
265
267
ILOGIC
IOB
IOBUF
IOBUFDS
IODELAY
ISERDES
L
LDT
LVCMOS
LVDCI
LVDS
LVPECL
LVTTL
primitive
REFCLK
IDDR
SR
switching characteristics
timing
defined
PULLUP/PULLDOWN/KEEPER
DATAIN
DATAOUT
IDATAIN
ODATAIN
ports
defined
attributes
bitslip
IDELAY
ports
primitive
serial-to-parallel converter
switching characteristics
timing models
width expansion
See HyperTransport
defined
defined
LVDCI_DV2
source termination
defined
LVDS_25_DCI
defined
defined
217
237
294
234
243
239
318
217
BITSLIP_ENABLE attribute
IDELAYCTRL
297
353
241
236
327
355
325
319
358
353
218
353
241
243
294
297
239
322
www.xilinx.com
,
318
337
,
338
327
354
358
,
372
327
327
356
327
,
244
343
,
363
295
367
361
303
337
296
324
363
353
,
362
M
multirate
N
NO_CHANGE mode
O
OBUF
OBUFDS
OBUFT
OBUFTDS
ODDR
OLOGIC
OSERDES
P
parallel-to-serial converter
PCI
PFDM
PLL
PSCLK
R
READ_FIRST mode
REFCLK
regional clock buffers
regional clocks
REV
RSDS
FIFO
PULLUP/PULLDOWN/KEEPER
clock forwarding
OPPOSITE_EDGE mode
ports
primitive
SAME_EDGE mode
timing
parallel-to-serial converter
switching characteristics
timing
DDR
SDR
247
allocation in device
clock buffers
clock nets
318
296
237
233
312
345
52
234
338
235
217
370
370
115
347
370
235
Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010
348
377
,
,
,
343
344
347
46
139
,
378
42
118
118
25
347
,
48
346
40
370
377
346
370