XC5VLX50T-1FFG665C Xilinx Inc, XC5VLX50T-1FFG665C Datasheet - Page 315

• Manufacturer Part Number: XC5VLX50T-1FFG665C
• Description: FPGA, VIRTEX-5 LXT, 50K, 665FCBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-5 LXTr

Specifications of XC5VLX50T-1FFG665C

• No. Of Logic Blocks: 7200
• Family Type: Virtex-5
• No. Of Speed Grades: 1
• Total Ram Bits: 2211840
• No. Of I/o's: 360
• Clock Management: DCM, PLL
• I/o Supply Voltage: 3.3V
• Operating Frequency Max: 550MHz
• Number Of Logic Elements/cells: 46080
• Number Of Labs/clbs: 3600
• Number Of I /o: 360
• Voltage - Supply: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 665-BBGA, FCBGA
• Core Supply Voltage Range: 1V
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: HW-V5-ML561-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML550-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML521-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5GBE-DK-UNI-G - KIT DEV V5 LXT GIGABIT ETHERNET122-1508 - EVALUATION PLATFORM VIRTEX-5
• Number Of Gates: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 122-1565

Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010
Full Device SSO Calculator
Other SSO Assumptions
LVDCI and HSLVDCI Drivers
Bank 0
A Microsoft Excel-based spreadsheet, the Virtex-5 FPGA SSO Calculator, automates all the
PFDM and SSO calculations. The Virtex-5 FPGA SSO calculator uses PCB geometry, (board
thickness, via diameter, and breakout trace width and length) to determine power system
inductance. It determines the smallest undershoot and logic-low threshold voltage among
all input devices, calculates the average output capacitance, and determines the SSO
allowance by taking into account all of the board-level design parameters mentioned in
this document. In addition, the Virtex-5 FPGA SSO calculator checks the adjacent bank and
package SSO ensuring the full device design does not exceed the SSO allowance. Since
bank-number assignment for Virtex-5 devices is different from package to package due to
its columnar architecture (versus the peripheral I/O architecture of previous devices),
there is a separate tab at the bottom of the SSO calculator display for each Virtex-5 FPGA
package. This customizing allows for the arrangement of physically adjacent banks (as
they appear clockwise on each unique package, even though they are not labeled in a
contiguous manner), and the hard-coding of the number of V
The Virtex-5 FPGA SSO Calculator file (ug190_SSO_Calculator.zip) is available at:
https://secure.xilinx.com/webreg/clickthrough.do?cid=30154.
All limits for controlled impedance DCI I/O standards assume a 50 Ω output impedance.
For higher reference resistor (RR) values, less drive strength is needed, and the SSO limit
increases linearly. To calculate the SSO limit for a controlled impedance driver with
different reference resistors, the following formula is used:
Example
The designer uses LVDCI_18 driver with 65 Ω reference resistors. The LVDCI_18 SSO limit
for 50 Ω impedance is first taken from
SSO per V
SSO Limit LVDCI_18 at 65 Ω = ((65 Ω)/50 Ω) × 11 = 14.3
Bank 0 in all devices contains only configuration and dedicated signals. Since there is no
user I/O in Bank 0, no SSO analysis is necessary for this bank.
User SSO
CCO
/GND pin pair. Therefore, the SSO limit for LVDCI_18 at 65 Ω is:
=
⎛
⎝
User RR
----------------------- - Ω
50Ω
www.xilinx.com
⎞ SSO Limit for Ω
⎠
(
Table
6-40. The SSO limit for LVDCI_18 at 50 Ω is 11
Simultaneous Switching Output Limits
)
CCO
/GND pairs per bank.
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