XC5VLX50T-1FFG665C Xilinx Inc, XC5VLX50T-1FFG665C Datasheet - Page 278

• Manufacturer Part Number: XC5VLX50T-1FFG665C
• Description: FPGA, VIRTEX-5 LXT, 50K, 665FCBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-5 LXTr

Specifications of XC5VLX50T-1FFG665C

• No. Of Logic Blocks: 7200
• Family Type: Virtex-5
• No. Of Speed Grades: 1
• Total Ram Bits: 2211840
• No. Of I/o's: 360
• Clock Management: DCM, PLL
• I/o Supply Voltage: 3.3V
• Operating Frequency Max: 550MHz
• Number Of Logic Elements/cells: 46080
• Number Of Labs/clbs: 3600
• Number Of I /o: 360
• Voltage - Supply: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 665-BBGA, FCBGA
• Core Supply Voltage Range: 1V
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: HW-V5-ML561-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML550-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML521-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5GBE-DK-UNI-G - KIT DEV V5 LXT GIGABIT ETHERNET122-1508 - EVALUATION PLATFORM VIRTEX-5
• Number Of Gates: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 122-1565

Chapter 6: SelectIO Resources
278
Figure 6-69
differential SSTL2 Class I (2.5V) with unidirectional DCI termination.
X-Ref Target - Figure 6-69
Table 6-29
Table 6-29: Differential SSTL2 Class I DC Voltage Specifications
Notes:
1. V
2. V
3. V
4. V
V
Input Parameters
V
V
V
V
V
Output Parameters
V
CCO
TT
IN
ID
ID
IX
OX
Figure 6-69: Differential SSTL2 (2.5V) Class I Unidirectional DCI Termination
DIFF_SSTL2_I_DCI
DIFF_SSTL2_I_DCI
DCI
IN
ID
IX
OX
(AC)
(DC)
(DC)
(AC)
(AC)
(AC) indicates the voltage where the differential input signals must cross.
(DC) specifies the allowable DC excursion of each differential input.
(DC) specifies the input differential voltage required for switching.
(AC) indicates the voltage where the differential output signals must cross.
R 0 = 25
R 0 = 25
(3)
(1)
(2)
(4)
lists the differential SSTL2 Class I DC voltage specifications.
shows a sample circuit illustrating a valid termination technique for
Ω
Ω
www.xilinx.com
Z 0
Z 0
IOB
V
V
CCO
CCO
2R
2R
2R
2R
= 2.5V
= 2.5V
VRP
VRN
VRP
VRN
–0.30
Min
0.62
0.95
2.3
0.3
1.0
–
= 2Z 0 = 100Ω
= 2Z 0 = 100Ω
= 2Z 0 = 100Ω
= 2Z 0 = 100Ω
V
CCO
Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010
Typ
2.5
–
–
–
–
–
× 0.5
DIFF_SSTL2_I_DCI
+
–
ug190_6_65_030506
V
V
V
CCO
CCO
CCO
Max
1.55
2.7
1.5
–
+ 0.30
+ 0.60
+ 0.60