XC5VLX50T-1FFG665C Xilinx Inc, XC5VLX50T-1FFG665C Datasheet - Page 152

FPGA, VIRTEX-5 LXT, 50K, 665FCBGA

XC5VLX50T-1FFG665C

Manufacturer Part Number
XC5VLX50T-1FFG665C
Description
FPGA, VIRTEX-5 LXT, 50K, 665FCBGA
Manufacturer
Xilinx Inc
Series
Virtex™-5 LXTr

Specifications of XC5VLX50T-1FFG665C

No. Of Logic Blocks
7200
Family Type
Virtex-5
No. Of Speed Grades
1
Total Ram Bits
2211840
No. Of I/o's
360
Clock Management
DCM, PLL
I/o Supply Voltage
3.3V
Operating Frequency Max
550MHz
Number Of Logic Elements/cells
46080
Number Of Labs/clbs
3600
Number Of I /o
360
Voltage - Supply
0.95 V ~ 1.05 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
665-BBGA, FCBGA
Core Supply Voltage Range
1V
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
HW-V5-ML561-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML550-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML521-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5GBE-DK-UNI-G - KIT DEV V5 LXT GIGABIT ETHERNET122-1508 - EVALUATION PLATFORM VIRTEX-5
Number Of Gates
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Other names
122-1565

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
XC5VLX50T-1FFG665C
Manufacturer:
Xilinx Inc
Quantity:
10 000
Part Number:
XC5VLX50T-1FFG665C
Manufacturer:
XILINX
0
Part Number:
XC5VLX50T-1FFG665C
Manufacturer:
XILINX
Quantity:
500
Part Number:
XC5VLX50T-1FFG665C
Quantity:
18
Part Number:
XC5VLX50T-1FFG665C
0
Part Number:
XC5VLX50T-1FFG665C4060
Manufacturer:
XILINX
Quantity:
1 122
Part Number:
XC5VLX50T-1FFG665C4060
Manufacturer:
XILINX
0
Part Number:
XC5VLX50T-1FFG665CES
Manufacturer:
Xilinx Inc
Quantity:
10 000
Chapter 4: Block RAM
152
Case 2: Writing to a Full or Almost Full FIFO
Clock Event 2 and Clock Event 4: Write Operation and Deassertion of Almost
EMPTY Signal
Three read-clock cycles after the fourth data is written into the FIFO, the Almost EMPTY
pin is deasserted to signify that the FIFO is not in the almost EMPTY state.
For the example in
event 2 is with respect to write-clock, while clock event 4 is with respect to read-clock.
Clock event 4 appears three read-clock cycles after clock event 2.
If the rising WRCLK edge is close to the rising RDCLK edge, AEMPTY could be deasserted
one RDCLK period later.
Prior to the operations performed in
example, the timing diagram reflects of both standard and FWFT modes.
X-Ref Target - Figure 4-22
WRERR
WRCLK
RDCLK
WREN
AFULL
RDEN
FULL
At time T
inputs of the FIFO.
Write enable remains asserted at the WREN input of the FIFO.
At clock event 4, DO output pins of the FIFO remains at 00 since no read has been
performed. In the case of standard mode, data 00 will never appear at the DO output
pins of the FIFO.
At time T
the AEMPTY pin. In the case of standard mode, AEMPTY deasserts in the same way
as in FWFT mode.
DI
FDCK_DI
FCKO_AEMPTY
Figure
Figure 4-22: Writing to a Full / Almost Full FIFO
1
00
, before clock event 2 (WRCLK), data 03 becomes valid at the DI
www.xilinx.com
4-21, the timing diagram is drawn to reflect FWFT mode. Clock
T
T
, after clock event 4 (RDCLK), almost empty is deasserted at
FCCK_WREN
FDCK_DI
01
Figure
T
FCKO_AFULL
02
4-22, the FIFO is almost completely full. In this
T
FDCK_DI
T
FCKO_FULL
03
T
FCKO_WERR
2
04
Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010
T
FCCK_WREN
T
FCKO_WERR
3
05
ug190_4_18_012605
T
FDCK_DI
4
06

Related parts for XC5VLX50T-1FFG665C