XC5VLX50T-1FFG665C Xilinx Inc, XC5VLX50T-1FFG665C Datasheet - Page 194

• Manufacturer Part Number: XC5VLX50T-1FFG665C
• Description: FPGA, VIRTEX-5 LXT, 50K, 665FCBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-5 LXTr

Specifications of XC5VLX50T-1FFG665C

• No. Of Logic Blocks: 7200
• Family Type: Virtex-5
• No. Of Speed Grades: 1
• Total Ram Bits: 2211840
• No. Of I/o's: 360
• Clock Management: DCM, PLL
• I/o Supply Voltage: 3.3V
• Operating Frequency Max: 550MHz
• Number Of Logic Elements/cells: 46080
• Number Of Labs/clbs: 3600
• Number Of I /o: 360
• Voltage - Supply: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 665-BBGA, FCBGA
• Core Supply Voltage Range: 1V
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: HW-V5-ML561-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML550-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML521-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5GBE-DK-UNI-G - KIT DEV V5 LXT GIGABIT ETHERNET122-1508 - EVALUATION PLATFORM VIRTEX-5
• Number Of Gates: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 122-1565

Chapter 5: Configurable Logic Blocks (CLBs)
194
X-Ref Target - Figure 5-20
It is possible to create shift registers longer than 128 bits across more than one SLICEM.
However, there are no direct connections between slices to form these shift registers.
Shift Register Data Flow
Shift Operation
The shift operation is a single clock-edge operation, with an active-High clock enable
feature. When enable is High, the input (D) is loaded into the first bit of the shift register.
Each bit is also shifted to the next highest bit position. In a cascadable shift register
configuration, the last bit is shifted out on the M31 output.
The bit selected by the 5-bit address port (A[4:0]) appears on the Q output.
Dynamic Read Operation
The Q output is determined by the 5-bit address. Each time a new address is applied to the
5-input address pins, the new bit position value is available on the Q output after the time
SHIFTIN (D)
A[6:0]
CLK
WE
(WE/CE)
Figure 5-20: 128-bit Shift Register Configuration
(CLK)
5
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DI1
A[6:2]
CLK
WE
DI1
A[6:2]
CLK
WE
DI1
A[6:2]
CLK
WE
DI1
A[6:2]
CLK
WE
SRL32
SRL32
SRL32
SRL32
MC31
MC31
MC31
MC31
O6
O6
O6
O6
(MC31)
F7BMUX
F7AMUX
CX (A5)
AX (A5)
SHIFTOUT (Q127)
BX (A6)
F8MUX
Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010
D Q
(BMUX)
(BQ)
(Optional)
UG190_5_20_050506
Output (Q)
Registered
Output