XC5VLX50T-1FFG665C Xilinx Inc, XC5VLX50T-1FFG665C Datasheet - Page 357

• Manufacturer Part Number: XC5VLX50T-1FFG665C
• Description: FPGA, VIRTEX-5 LXT, 50K, 665FCBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-5 LXTr

Specifications of XC5VLX50T-1FFG665C

• No. Of Logic Blocks: 7200
• Family Type: Virtex-5
• No. Of Speed Grades: 1
• Total Ram Bits: 2211840
• No. Of I/o's: 360
• Clock Management: DCM, PLL
• I/o Supply Voltage: 3.3V
• Operating Frequency Max: 550MHz
• Number Of Logic Elements/cells: 46080
• Number Of Labs/clbs: 3600
• Number Of I /o: 360
• Voltage - Supply: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 665-BBGA, FCBGA
• Core Supply Voltage Range: 1V
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: HW-V5-ML561-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML550-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML521-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5GBE-DK-UNI-G - KIT DEV V5 LXT GIGABIT ETHERNET122-1508 - EVALUATION PLATFORM VIRTEX-5
• Number Of Gates: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 122-1565

Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010
High-Speed Clock Input - CLK
High-Speed Clock Input - CLKB
Divided Clock Input - CLKDIV
Serial Input Data from IOB - D
High-Speed Clock for Strobe-Based Memory Interfaces - OCLK
Reset Input - RST
registers FF0, FF1, FF2, and FF3 shown in
Figure 8-13, page 369
The clock enable module functions as a 2:1 serial-to-parallel converter, clocked by CLKDIV.
The clock enable module is needed specifically for bidirectional memory interfaces when
ISERDES_NODELAY is configured for 1:4 deserialization in DDR mode. When the
attribute NUM_CE = 2, the clock enable module is enabled and both CE1 and CE2 ports
are available. When NUM_CE = 1, only CE1 is available and functions as a regular clock
enable.
The high-speed clock input (CLK) is used to clock in the input serial data stream.
The high-speed secondary clock input (CLKB) is used to clock in the input serial data
stream. CLKB should be connected to CLK in both SDR and DDR mode.
The divided clock input (CLKDIV) is typically a divided version of CLK (depending on the
width of the implemented deserialization). It drives the output of the serial-to-parallel
converter, the Bitslip submodule, and the CE module.
The serial input data port (D) is the serial (high-speed) data input port of the
ISERDES_NODELAY. This port works in conjunction with all the Virtex-5 FPGA I/O
resources to accommodate the desired I/O standards.
The OCLK clock input synchronizes data transfer in strobe-based memory interfaces. The
OCLK of the ISERDES_NODELAY shares the same routing as the CLK port of the
OSERDES.
The OCLK clock input is used to transfer strobe-based memory data onto a free-running
clock domain. OCLK is a free-running FPGA clock at the same frequency as the strobe on
the CLK input. The domain transfer from CLK to OCLK is shown in the
diagram. The timing of the domain transfer is set by the user by adjusting the delay of the
strobe signal to the CLK input (e.g., using IDELAY). Examples of setting the timing of this
domain transfer are given in several memory-related application notes, including
XAPP858: High-Performance DDR2 SDRAM Interface in Virtex-5 Devices. When
INTERFACE_TYPE is NETWORKING, this port is unused.
The reset input causes the outputs of all data flip-flops in the CLK and CLKDIV domains
to be driven Low asynchronously. ISERDES_NODELAY circuits running in the CLK
domain where timing is critical use an internal, dedicated circuit to retime the RST input to
produce a reset signal synchronous to the CLK domain. Similarly, there is a dedicated
circuit to retime the RST input to produce a reset signal synchronous to the CLKDIV
domain. Because there are ISERDES_NODELAY circuits that retime the RST input, the user
is only required to provide a reset pulse to the RST input that meets timing on the CLKDIV
do not have clock enable inputs.
www.xilinx.com
Input Serial-to-Parallel Logic Resources (ISERDES)
Figure 8-12, page
368. The remaining registers in
Figure 8-5
block
357