XC5VLX50T-1FFG665C Xilinx Inc, XC5VLX50T-1FFG665C Datasheet - Page 111

• Manufacturer Part Number: XC5VLX50T-1FFG665C
• Description: FPGA, VIRTEX-5 LXT, 50K, 665FCBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-5 LXTr

Specifications of XC5VLX50T-1FFG665C

• No. Of Logic Blocks: 7200
• Family Type: Virtex-5
• No. Of Speed Grades: 1
• Total Ram Bits: 2211840
• No. Of I/o's: 360
• Clock Management: DCM, PLL
• I/o Supply Voltage: 3.3V
• Operating Frequency Max: 550MHz
• Number Of Logic Elements/cells: 46080
• Number Of Labs/clbs: 3600
• Number Of I /o: 360
• Voltage - Supply: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 665-BBGA, FCBGA
• Core Supply Voltage Range: 1V
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: HW-V5-ML561-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML550-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML521-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5GBE-DK-UNI-G - KIT DEV V5 LXT GIGABIT ETHERNET122-1508 - EVALUATION PLATFORM VIRTEX-5
• Number Of Gates: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 122-1565

PLL in Virtex-4 FPGA PMCD Legacy Mode
Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010
Virtex-5 devices do not have Phase-Matched Clock Dividers (PMCDs). The Virtex-5 FPGA
PLL supports the Virtex-4 FPGA PMCD mode of operation. To take advantage of the
inherently more powerful features of the Virtex-5 FPGA PLL, Xilinx recommends
redesigning Virtex-4 FPGA PMCDs by implementing PLLs directly. The difference
between the Virtex-5 FPGA PLL and the Virtex-4 FPGA PMCD block in Virtex-4 FPGA
PMCD legacy mode is that only two clock inputs are supported in the Virtex-5 device
implementation. The Virtex-4 device implementation supported up to four clock inputs. If
four clock inputs must be used, then two PLLs can be put into PMCD mode. In this case,
delay matching is not optimal.
Figure 3-17
can not be used as a PLL if it is already being used as a PMCD. To design-in the Virtex-5
FPGA PMCD functionality, instantiate a Virtex-4 FPGA PMCD primitive. ISE software
maps the Virtex-4 FPGA PMCD primitive into a Virtex-5 FPGA PLL.
X-Ref Target - Figure 3-17
Table 3-8
the Virtex-4 FPGA PMCD port names.
Table 3-8: Mapping of Port Names
Figure 3-17: PMCD Primitive Implemented Using the PLL in PMCD Legacy Mode
Virtex-4 FPGA
Port Name
CLKA1D2
CLKA1D4
CLKA1D8
CLKA1
shows the port mapping between Virtex-5 FPGA PLL in PMCD legacy mode and
CLKA
CLKD
CLKC
CLKB
shows the Virtex-4 FPGA PMCD primitive implemented using a PLL. A PLL
CLKFBIN
CLKIN
www.xilinx.com
Virtex-5 FPGA
Port Name
CLKOUT3
CLKOUT2
CLKOUT1
CLKOUT0
CLKFBIN
CLKIN
n/a
n/a
CLKFBOUT
PLL in Virtex-4 FPGA PMCD Legacy Mode
O0
O1
O2
O3
ug190_3_16_022207
To BUFG
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