XC5VLX50T-1FFG665C Xilinx Inc, XC5VLX50T-1FFG665C Datasheet - Page 48

• Manufacturer Part Number: XC5VLX50T-1FFG665C
• Description: FPGA, VIRTEX-5 LXT, 50K, 665FCBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-5 LXTr

Specifications of XC5VLX50T-1FFG665C

• No. Of Logic Blocks: 7200
• Family Type: Virtex-5
• No. Of Speed Grades: 1
• Total Ram Bits: 2211840
• No. Of I/o's: 360
• Clock Management: DCM, PLL
• I/o Supply Voltage: 3.3V
• Operating Frequency Max: 550MHz
• Number Of Logic Elements/cells: 46080
• Number Of Labs/clbs: 3600
• Number Of I /o: 360
• Voltage - Supply: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 665-BBGA, FCBGA
• Core Supply Voltage Range: 1V
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: HW-V5-ML561-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML550-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML521-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5GBE-DK-UNI-G - KIT DEV V5 LXT GIGABIT ETHERNET122-1508 - EVALUATION PLATFORM VIRTEX-5
• Number Of Gates: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 122-1565

Chapter 2: Clock Management Technology
Table 2-1: Available CMT, DCM, and PLL Resources
DCM Summary
48
XC5VLX20T
XC5VLX30
XC5VFX30T
XC5VLX30T
XC5VSX35T
XC5VLX50
XC5VLX50T
XC5VSX50T
XC5VFX70T
XC5VLX85
XC5VLX85T
XC5VSX95T
XC5VFX100T
XC5VLX110
XC5VLX110T
XC5VFX130T
XC5VTX150T
XC5VLX155
XC5VLX155T
XC5VFX200T
XC5VLX220
XC5VLX220T
XC5VSX240T
XC5VTX240T
XC5VLX330
XC5VLX330T
Device
Number of
CMTs
Table 2-1
The Digital Clock Managers (DCMs) in Virtex-5 FPGAs provide a wide range of powerful
clock management features:
•
1
2
6
Clock Deskew
The DCM contains a delay-locked loop (DLL) to completely eliminate clock
distribution delays, by deskewing the DCM's output clocks with respect to the input
clock. The DLL contains delay elements (individual small buffers) and control logic.
The incoming clock drives a chain of delay elements, thus the output of every delay
element represents a version of the incoming clock delayed at a different point.
The control logic contains a phase detector and a delay-line selector. The phase
detector compares the incoming clock signal (CLKIN) against a feedback input
(CLKFB) and steers the delay line selector, essentially adding delay to the output of
DCM until the CLKIN and CLKFB coincide.
summarizes the availability of CMTs, DCMs, and PLLs in each Virtex-5 device.
Available
DCMs
12
2
4
Bottom half:
DCM_ADV_X0Y0, DCM_ADV_X0Y1, PLL_ADV_X0Y0
Bottom half:
DCM_ADV_X0Y0, DCM_ADV_X0Y1, PLL_ADV_X0Y0
Top half:
DCM_ADV_X0Y2, DCM_ADV_X0Y3, PLL_ADV_X0Y1
Bottom half:
DCM_ADV_X0Y0, DCM_ADV_X0Y1, PLL_ADV_X0Y0
DCM_ADV_X0Y2, DCM_ADV_X0Y3, PLL_ADV_X0Y1
DCM_ADV_X0Y4, DCM_ADV_X0Y5, PLL_ADV_X0Y2
Top half:
DCM_ADV_X0Y6, DCM_ADV_X0Y7, PLL_ADV_X0Y3
DCM_ADV_X0Y8, DCM_ADV_X0Y9, PLL_ADV_X0Y4
DCM_ADV_X0Y10, DCM_ADV_X0Y11, PLL_ADV_X0Y5
www.xilinx.com
Site Names
Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010