FPGA, VIRTEX-5 LXT, 50K, 665FCBGA

XC5VLX50T-1FFG665C

Manufacturer Part NumberXC5VLX50T-1FFG665C
DescriptionFPGA, VIRTEX-5 LXT, 50K, 665FCBGA
ManufacturerXilinx Inc
SeriesVirtex™-5 LXT
XC5VLX50T-1FFG665C datasheets
Product Change Notification
 


Specifications of XC5VLX50T-1FFG665C

No. Of Logic Blocks7200Family TypeVirtex-5
No. Of Speed Grades1Total Ram Bits2211840
No. Of I/o's360Clock ManagementDCM, PLL
I/o Supply Voltage3.3VOperating Frequency Max550MHz
Number Of Logic Elements/cells46080Number Of Labs/clbs3600
Number Of I /o360Voltage - Supply0.95 V ~ 1.05 V
Mounting TypeSurface MountOperating Temperature0°C ~ 85°C
Package / Case665-BBGA, FCBGACore Supply Voltage Range1V
Rohs CompliantYesLead Free Status / RoHS StatusLead free / RoHS Compliant
For Use WithHW-V5-ML561-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML550-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML521-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5GBE-DK-UNI-G - KIT DEV V5 LXT GIGABIT ETHERNET122-1508 - EVALUATION PLATFORM VIRTEX-5Number Of Gates-
Other names122-1565  
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Table 68: Block RAM and FIFO Switching Characteristics (Cont’d)
Symbol
Reset Delays
T
Reset RST to FIFO Flags/Pointers
RCO_FLAGS
Maximum Frequency
F
Block RAM in all modes
MAX
F
Block RAM in cascade configuration
MAX_CASCADE
F
FIFO in all modes
MAX_FIFO
F
Block RAM and FIFO in ECC configuration
MAX_ECC
Notes:
1.
TRACE will report all of these parameters as T
2.
T
includes T
, T
RCKO_DOR
RCKO_DOW
RCKO_DOPR
3.
These parameters also apply to synchronous FIFO with DO_REG = 0.
4.
T
includes T
as well as the B port equivalent timing parameters.
RCKO_DO
RCKO_DOP
5.
These parameters also apply to multirate (asynchronous) and synchronous FIFO with DO_REG = 1.
6.
T
includes the following parameters: T
RCKO_FLAGS
7.
T
includes both T
RCKO_POINTERS
RCKO_RDCOUNT
8.
The ADDR setup and hold must be met when EN is asserted even though WE is deasserted. Otherwise, block RAM data corruption is possible.
9.
T
includes both A and B inputs as well as the parity inputs of A and B.
RCKO_DI
10.
These parameters also apply to RDEN.
11.
T
includes the following flags: AEMPTY, AFULL, EMPTY, FULL, RDERR, WRERR, RDCOUNT, and WRCOUNT.
RCO_FLAGS
DSP48E Switching Characteristics
Table 69: DSP48E Switching Characteristics
Symbol
Setup and Hold Times of Data/Control Pins to the Input Register Clock
TDSPDCK_{AA, BB, ACINA, BCINB}/
TDSPCKD_{AA, BB, ACINA, BCINB}
TDSPDCK_CC/TDSPCKD_CC
Setup and Hold Times of Data Pins to the Pipeline Register Clock
TDSPDCK_{AM, BM, ACINM, BCINM}/
TDSPCKD_{AM, BM, ACINM, BCINM}
Setup and Hold Times of Data/Control Pins to the Output Register Clock
TDSPDCK_{AP, BP, ACINP, BCINP}_M/
TDSPCKD_{AP, BP, ACINP, BCINP}_M
TDSPDCK_{AP, BP, ACINP, BCINP}_NM/
TDSPCKD_{AP, BP, ACINP, BCINP}_NM
TDSPDCK_CP/TDSPCKD_CP
TDSPDCK_{PCINP, CRYCINP, MULTSIGNINP}/
TDSPCKD_{PCINP, CRYCINP, MULTSIGNINP}
Setup and Hold Times of the CE Pins
TDSPCCK_{CEA1A, CEA2A, CEB1B, CEB2B}/
TDSPCKC_{CEA1A, CEA2A, CEB1A, CEB2B}
TDSPCCK_CECC/TDSPCKC_CECC
DS202 (v5.3) May 5, 2010
Product Specification
Virtex-5 FPGA Data Sheet: DC and Switching Characteristics
Description
(11)
.
RCKO_DO
, and T
as well as the B port equivalent timing parameters.
RCKO_DOPW
, T
, T
RCKO_AEMPTY
RCKO_AFULL
RCKO_EMPTY
and T
RCKO_WRCOUNT.
Description
{A, B, ACIN, BCIN} input to {A, B}
register CLK
C input to C register CLK
{A, B, ACIN, BCIN} input to M register
CLK
{A, B, ACIN, BCIN} input to P register
CLK using multiplier
{A, B, ACIN, BCIN} input to P register
CLK not using multiplier
C input to P register CLK
{PCIN, CARRYCASCIN, MULTSIGNIN}
input to P register CLK
{CEA1, CEA2A, CEB1B, CEB2B} input
to {A, B} register CLK
CEC input to C register CLK
www.xilinx.com
Speed Grade
-3
-2
-1
1.10
1.26
1.48
550
500
450
500
450
400
550
500
450
415
375
325
, T
, T
, T
RCKO_FULL
RCKO_RDERR
RCKO_WRERR.
Speed
-3
-2
-1
0.17
0.21
0.26
0.17
0.23
0.30
0.14
0.16
0.20
0.26
0.31
0.37
1.30
1.44
1.71
0.19
0.19
0.19
2.39
2.74
3.25
–0.30
–0.30
–0.30
1.35
1.54
1.83
–0.10
–0.10
–0.10
1.30
1.42
1.70
–0.13
–0.13
–0.13
1.06
1.17
1.31
0.11
0.11
0.11
0.24
0.28
0.33
0.21
0.25
0.31
0.19
0.21
0.26
0.17
0.21
0.28
Units
ns, Max
MHz
MHz
MHz
MHz
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
48