FPGA, VIRTEX-5 LXT, 50K, 665FCBGA

XC5VLX50T-1FFG665C

Manufacturer Part NumberXC5VLX50T-1FFG665C
DescriptionFPGA, VIRTEX-5 LXT, 50K, 665FCBGA
ManufacturerXilinx Inc
SeriesVirtex™-5 LXT
XC5VLX50T-1FFG665C datasheets
Product Change Notification
 


Specifications of XC5VLX50T-1FFG665C

No. Of Logic Blocks7200Family TypeVirtex-5
No. Of Speed Grades1Total Ram Bits2211840
No. Of I/o's360Clock ManagementDCM, PLL
I/o Supply Voltage3.3VOperating Frequency Max550MHz
Number Of Logic Elements/cells46080Number Of Labs/clbs3600
Number Of I /o360Voltage - Supply0.95 V ~ 1.05 V
Mounting TypeSurface MountOperating Temperature0°C ~ 85°C
Package / Case665-BBGA, FCBGACore Supply Voltage Range1V
Rohs CompliantYesLead Free Status / RoHS StatusLead free / RoHS Compliant
For Use WithHW-V5-ML561-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML550-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML521-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5GBE-DK-UNI-G - KIT DEV V5 LXT GIGABIT ETHERNET122-1508 - EVALUATION PLATFORM VIRTEX-5Number Of Gates-
Other names122-1565  
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Page 91
Page 91/91

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Prev
Date
Version
12/02/08
4.8
• Added I
• In
Table 32, page
• Changed Conditions for T
• In
Table 35, page
• In
Table 45, page
• In
Table 46, page
• In
Table 54, page
• In
Table 55, page
• In
Table 58, page
• In
Table 59, page
• In
Table 80, page
12/19/08
4.9
• Updated
XC5VFX100T, and XC5VFX200T devices.
01/14/09
4.10
• In
Table 1, page
• In
Table 54, page
Production.
• In
Table 55, page
• In
Table 80, page
T
DUTY_CYC_DLL
02/06/09
5.0
• Changed document classification from Advance Product Specification to Product Specification.
• In
Table 1, page
• In
Table 5, page
current.
• In
Table 74, page
04/01/09
5.1
• In
Table 65, page
• In
Table 74, page
06/25/09
5.2
• In
Table 2, page
• In
Table 11, page
05/05/10
5.3
Removed DV
In
Table
31, changed “GTPDRPCLK” to “GTP DCLK (DRP clock)” in the Description column. In
added table note 2 about R
In
Table
41, changed the maximum value of V
In
Table
42, changed the minimum PLL frequency (F
Table
43, changed “GTXDRPCLK” to “GTX DCLK (DRP clock)” in the Description column. In
removed “2 byte or 4 byte interface” from the Conditions column for T
note 2 about R
In
Table
51, changed the maximum value of AI
In
Table
74, updated description of T
Notice of Disclaimer
THE XILINX HARDWARE FPGA AND CPLD DEVICES REFERRED TO HEREIN ("PRODUCTS") ARE SUBJECT TO THE TERMS AND
CONDITIONS OF THE XILINX LIMITED WARRANTY WHICH CAN BE VIEWED AT http://www.xilinx.com/warranty.htm. THIS LIMITED
WARRANTY DOES NOT EXTEND TO ANY USE OF PRODUCTS IN AN APPLICATION OR ENVIRONMENT THAT IS NOT WITHIN THE
SPECIFICATIONS STATED IN THE XILINX DATA SHEET. ALL SPECIFICATIONS ARE SUBJECT TO CHANGE WITHOUT NOTICE.
PRODUCTS ARE NOT DESIGNED OR INTENDED TO BE FAIL-SAFE OR FOR USE IN ANY APPLICATION REQUIRING FAIL-SAFE
PERFORMANCE, SUCH AS LIFE-SUPPORT OR SAFETY DEVICES OR SYSTEMS, OR ANY OTHER APPLICATION THAT INVOKES
THE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR PROPERTY OR ENVIRONMENTAL DAMAGE ("CRITICAL
APPLICATIONS"). USE OF PRODUCTS IN CRITICAL APPLICATIONS IS AT THE SOLE RISK OF CUSTOMER, SUBJECT TO
APPLICABLE LAWS AND REGULATIONS.
DS202 (v5.3) May 5, 2010
Product Specification
Virtex-5 FPGA Data Sheet: DC and Switching Characteristics
Revision
row to Absolute Maximum Ratings in
IN
16, changed duty cycle values for T
in
Table 32, page 16
PHASE
18, updated R
values, updated note 1, and added note 2.
XPPMTOL
23, updated parameters with separate FXT and TXT values.
23, corrected units of T
LLSKEW
30, updated SX240T, FXT, and TXT speed grade designations.
31, updated SX240T and FXT rows.
37, added LVCMOS, 1.2V row.
38, corrected V
value for LVCMOS, 1.2V row.
MEAS
60, updated note 3 with sentence about global clock tree.
Table 5, page 6
with power-on current values for XC5VSX240T, XC5VTX150T, XC5VTX240T,
1, changed note 2 to refer to UG112 for soldering guidelines.
30, moved speed grades for the XC5VTX150T and XC5VTX240T devices to
31, added the ISE software version for the XC5VTX150T and XC5VTX240T devices.
60, moved the reference to the duty cycle distortion note to apply to both
and T
.
DUTY_CYC_FX
1, changed V
and added note 5.
IN
6, removed the Max columns and added note 2 about calculating the maximum startup
55, removed LX20T from second row of F
44, changed “A – D input” to “AX – DX input” for the T
55, prepended “±” to all speed grade values for the T
2, added note 6.
9, changed V
to V
CCAUX
CCO
from the examples in
Figure 2
and
PPIN
.
XPPMTOL
to 1000 mV.
ISE
.
XPPMTOL
to 13 mA.
DD
.
FBDELAY
www.xilinx.com
Table 1, page
1.
and added note 2.
DCREF
and
Table 44, page
22.
.
.
OUTMAX
/T
parameter.
DICK
CKDI
parameter.
OUTDUTY
in note 1.
Figure
7.
) to 1.48 GHz for all three speed grades. In
GPLLMIN
and T
. In
Table
RX
TX
Table
35,
Table
45,
47, added table
91