FPGA, VIRTEX-5 LXT, 50K, 665FCBGA

XC5VLX50T-1FFG665C

Manufacturer Part NumberXC5VLX50T-1FFG665C
DescriptionFPGA, VIRTEX-5 LXT, 50K, 665FCBGA
ManufacturerXilinx Inc
SeriesVirtex™-5 LXT
XC5VLX50T-1FFG665C datasheets
Product Change Notification
 


Specifications of XC5VLX50T-1FFG665C

No. Of Logic Blocks7200Family TypeVirtex-5
No. Of Speed Grades1Total Ram Bits2211840
No. Of I/o's360Clock ManagementDCM, PLL
I/o Supply Voltage3.3VOperating Frequency Max550MHz
Number Of Logic Elements/cells46080Number Of Labs/clbs3600
Number Of I /o360Voltage - Supply0.95 V ~ 1.05 V
Mounting TypeSurface MountOperating Temperature0°C ~ 85°C
Package / Case665-BBGA, FCBGACore Supply Voltage Range1V
Rohs CompliantYesLead Free Status / RoHS StatusLead free / RoHS Compliant
For Use WithHW-V5-ML561-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML550-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML521-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5GBE-DK-UNI-G - KIT DEV V5 LXT GIGABIT ETHERNET122-1508 - EVALUATION PLATFORM VIRTEX-5Number Of Gates-
Other names122-1565  
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
Page 51
52
Page 52
53
Page 53
54
Page 54
55
Page 55
56
Page 56
57
Page 57
58
Page 58
59
Page 59
60
Page 60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
Page 51/91

Download datasheet (3Mb)Embed
PrevNext
Configuration Switching Characteristics
Table 70: Configuration Switching Characteristics
Symbol
Power-up Timing Characteristics
T
PL
T
POR
T
ICCK
T
PROGRAM
Master/Slave Serial Mode Programming Switching
T
/T
DCCK
CCKD
T
/T
DSCCK
SCCKD
T
CCO
F
MCCK
F
MCCKTOL
F
MSCCK
SelectMAP Mode Programming Switching
T
/T
SMDCCK
SMCCKD
T
/T
SMCSCCK
SMCCKCS
T
/T
SMCCKW
SMWCCK
T
SMCKCSO
T
SMCO
T
SMCKBY
F
SMCCK
F
RBCCK
F
MCCKTOL
Boundary-Scan Port Timing Specifications
T
TAPTCK
T
TCKTAP
T
TCKTDO
F
TCK
F
TCKB
DS202 (v5.3) May 5, 2010
Product Specification
Virtex-5 FPGA Data Sheet: DC and Switching Characteristics
Description
Program Latency
Power-on-Reset
CCLK (output) delay
Program Pulse Width
(1)
DIN Setup/Hold, slave mode
DIN Setup/Hold, master mode
DOUT
Maximum Frequency, master mode with
respect to nominal CCLK.
Frequency Tolerance, master mode with
respect to nominal CCLK.
Slave mode external CCLK
(1)
SelectMAP Data Setup/Hold
CS_B Setup/Hold
RDWR_B Setup/Hold
CSO_B clock to out
(330 Ω pull-up resistor required)
CCLK to DATA out in readback
CCLK to BUSY out in readback
Maximum Frequency with respect to nominal
CCLK.
Maximum Readback Frequency with respect
to nominal CCLK
Frequency Tolerance with respect to nominal
CCLK.
TMS and TDI Setup time before TCK
TMS and TDI Hold time after TCK
TCK falling edge to TDO output valid
Maximum configuration TCK clock frequency
Maximum boundary-scan TCK clock
frequency
www.xilinx.com
Speed Grade
Units
-3
-2
-1
3
3
3
ms, Max
10
10
10
ms, Min/Max
50
50
50
400
400
400
ns, Min
250
250
250
ns, Min
4.0
4.0
4.0
ns, Min
0.0
0.0
0.0
4.0
4.0
4.0
ns, Min
0.0
0.0
0.0
7.5
7.5
7.5
ns, Max
100
100
100
MHz,
Max
±50
±50
±50
%
100
100
100
MHz
3.0
3.0
3.0
ns, Min
0.5
0.5
0.5
3.0
3.0
3.0
ns, Min
0.5
0.5
0.5
8.0
8.0
8.0
ns, Min
0.5
0.5
0.5
10
10
10
ns, Min
9.0
9.0
9.0
ns, Max
7.5
7.5
7.5
ns, Max
100
100
100
MHz, Max
60
60
60
MHz, Max
±50
±50
±50
%
1.0
1.0
1.0
ns, Min
2.0
2.0
2.0
ns, Min
6
6
6
ns, Max
66
66
66
MHz, Max
66
66
66
MHz, Max
51