FPGA, VIRTEX-5 LXT, 50K, 665FCBGA

XC5VLX50T-1FFG665C

Manufacturer Part NumberXC5VLX50T-1FFG665C
DescriptionFPGA, VIRTEX-5 LXT, 50K, 665FCBGA
ManufacturerXilinx Inc
SeriesVirtex™-5 LXT
XC5VLX50T-1FFG665C datasheets
Product Change Notification
 


Specifications of XC5VLX50T-1FFG665C

No. Of Logic Blocks7200Family TypeVirtex-5
No. Of Speed Grades1Total Ram Bits2211840
No. Of I/o's360Clock ManagementDCM, PLL
I/o Supply Voltage3.3VOperating Frequency Max550MHz
Number Of Logic Elements/cells46080Number Of Labs/clbs3600
Number Of I /o360Voltage - Supply0.95 V ~ 1.05 V
Mounting TypeSurface MountOperating Temperature0°C ~ 85°C
Package / Case665-BBGA, FCBGACore Supply Voltage Range1V
Rohs CompliantYesLead Free Status / RoHS StatusLead free / RoHS Compliant
For Use WithHW-V5-ML561-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML550-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML521-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5GBE-DK-UNI-G - KIT DEV V5 LXT GIGABIT ETHERNET122-1508 - EVALUATION PLATFORM VIRTEX-5Number Of Gates-
Other names122-1565  
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
Page 41
42
Page 42
43
Page 43
44
Page 44
45
Page 45
46
Page 46
47
Page 47
48
Page 48
49
Page 49
50
Page 50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
Page 43/91

Download datasheet (3Mb)Embed
PrevNext
Output Serializer/Deserializer Switching Characteristics
Table 63: OSERDES Switching Characteristics
Symbol
Setup/Hold
T
/T
D input Setup/Hold with respect to CLKDIV
OSDCK_D
OSCKD_D
(1)
T
/T
T input Setup/Hold with respect to CLK
OSDCK_T
OSCKD_T
(1)
T
/T
T input Setup/Hold with respect to CLKDIV
OSDCK_T2
OSCKD_T2
T
/T
OCE input Setup/Hold with respect to CLK
OSCCK_OCE
OSCKC_OCE
T
SR (Reset) input Setup with respect to CLKDIV
OSCCK_S
T
/T
TCE input Setup/Hold with respect to CLK
OSCCK_TCE
OSCKC_TCE
Sequential Delays
T
Clock to out from CLK to OQ
OSCKO_OQ
T
Clock to out from CLK to TQ
OSCKO_TQ
Combinatorial
T
T input to TQ Out
OSDO_TTQ
T
Asynchronous Reset to OQ
OSCO_OQ
T
Asynchronous Reset to TQ
OSCO_TQ
Notes:
1.
T
and T
are reported as T
OSDCK_T2
OSCKD_T2
DS202 (v5.3) May 5, 2010
Product Specification
Virtex-5 FPGA Data Sheet: DC and Switching Characteristics
Description
/T
in TRACE report.
OSDCK_T
OSCKD_T
www.xilinx.com
Speed Grade
Units
-3
-2
-1
0.21
0.24
0.30
ns
–0.02
–0.02
–0.02
0.28
0.34
0.41
ns
–0.18
–0.18
–0.18
0.21
0.24
0.28
ns
–0.03
–0.03
–0.03
0.16
0.19
0.23
ns
–0.07
–0.07
–0.07
0.52
0.58
0.70
ns
0.20
0.23
0.29
ns
–0.06
–0.06
–0.06
0.59
0.60
0.61
ns
0.61
0.62
0.62
ns
0.62
0.70
0.83
ns
1.57
1.82
2.19
ns
1.63
1.89
2.27
ns
43