FPGA, VIRTEX-5 LXT, 50K, 665FCBGA

XC5VLX50T-1FFG665C

Manufacturer Part NumberXC5VLX50T-1FFG665C
DescriptionFPGA, VIRTEX-5 LXT, 50K, 665FCBGA
ManufacturerXilinx Inc
SeriesVirtex™-5 LXT
XC5VLX50T-1FFG665C datasheets
Product Change Notification
 


Specifications of XC5VLX50T-1FFG665C

No. Of Logic Blocks7200Family TypeVirtex-5
No. Of Speed Grades1Total Ram Bits2211840
No. Of I/o's360Clock ManagementDCM, PLL
I/o Supply Voltage3.3VOperating Frequency Max550MHz
Number Of Logic Elements/cells46080Number Of Labs/clbs3600
Number Of I /o360Voltage - Supply0.95 V ~ 1.05 V
Mounting TypeSurface MountOperating Temperature0°C ~ 85°C
Package / Case665-BBGA, FCBGACore Supply Voltage Range1V
Rohs CompliantYesLead Free Status / RoHS StatusLead free / RoHS Compliant
For Use WithHW-V5-ML561-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML550-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML521-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5GBE-DK-UNI-G - KIT DEV V5 LXT GIGABIT ETHERNET122-1508 - EVALUATION PLATFORM VIRTEX-5Number Of Gates-
Other names122-1565  
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Table 46: GTX_DUAL Tile Transmitter Switching Characteristics (Cont’d)
Symbol
(2)
T
Total Jitter
J3.75
D
Deterministic Jitter
J3.75
(2)
T
Total Jitter
J3.2
D
Deterministic Jitter
J3.2
(2)
T
Total Jitter
J3.2L
D
Deterministic Jitter
J3.2L
(2)
T
Total Jitter
J2.5
D
Deterministic Jitter
J2.5
(2)
T
Total Jitter
J1.25
D
Deterministic Jitter
J1.25
(2)(4)
T
Total Jitter
J750
D
Deterministic Jitter
J750
(2)(4)
T
Total Jitter
J150
D
Deterministic Jitter
J150
Notes:
1.
Using same REFCLK input with TXENPMAPHASEALIGN enabled for up to four consecutive GTX_DUAL sites.
2.
Using PLL_DIVSEL_FB = 2, INTDATAWIDTH = 1. These values are NOT intended for protocol specific compliance determinations.
3.
PLL frequency at 1.6 GHz and OUTDIV = 1.
4.
GREFCLK can be used for serial data rates up to 1.0 Gb/s, but performance is not guaranteed.
Table 47: GTX_DUAL Tile Receiver Switching Characteristics
Symbol
F
Serial data rate
GTXRX
TIme for RXELECIDLE to
T
respond to loss or
RXELECIDLE
restoration of data
OOB detect threshold
R
XOOBVDPP
peak-to-peak
Receiver spread-spectrum
R
XSST
(1)
tracking
R
Run length (CID)
XRL
Data/REFCLK PPM offset
R
XPPMTOL
(2)
tolerance
(3)
SJ Jitter Tolerance
JT_SJ
Sinusoidal Jitter
6.5
JT_SJ
Sinusoidal Jitter
5.0
JT_SJ
Sinusoidal Jitter
4.25
JT_SJ
Sinusoidal Jitter
3.75
JT_SJ
Sinusoidal Jitter
3.2
JT_SJ
Sinusoidal Jitter
3.2L
JT_SJ
Sinusoidal Jitter
2.5
JT_SJ
Sinusoidal Jitter
1.25
DS202 (v5.3) May 5, 2010
Product Specification
Virtex-5 FPGA Data Sheet: DC and Switching Characteristics
Description
Condition
3.75 Gb/s
(2)
3.2 Gb/s
(2)
3.2 Gb/s
(2)
2.5 Gb/s
(2)
1.25 Gb/s
(2)
750 Mb/s
(2)(4)
150 Mb/s
(2)(4)
Description
RX oversampler not enabled
RX oversampler enabled
OOBDETECT_THRESHOLD = 110
OOBDETECT_THRESHOLD = 110
Modulated @ 33 KHz
Internal AC capacitor bypassed
nd
CDR 2
-order loop disabled
nd
CDR 2
-order loop enabled
(4)
6.5 Gb/s
(4)
5.0 Gb/s
(4)
4.25 Gb/s
(4)
3.75 Gb/s
(4)
3.2 Gb/s
(4)
(5)
3.2 Gb/s
(4)
2.5 Gb/s
(4)
1.25 Gb/s
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Min
Typ
Max
0.34
0.16
0.20
0.10
(3)
0.36
0.16
0.20
0.08
0.15
0.06
0.10
0.03
0.02
0.01
Min
Typ
Max
0.75
F
GTXMAX
0.15
0.75
75
55
135
–5000
0
512
–200
200
–2000
2000
0.44
0.44
0.44
0.44
0.45
0.45
0.50
0.50
Units
UI
UI
UI
UI
UI
UI
UI
UI
UI
UI
UI
UI
UI
UI
Units
Gb/s
Gb/s
ns
mV
ppm
UI
ppm
ppm
UI
UI
UI
UI
UI
UI
UI
UI
24