FPGA, VIRTEX-5 LXT, 50K, 665FCBGA

XC5VLX50T-1FFG665C

Manufacturer Part NumberXC5VLX50T-1FFG665C
DescriptionFPGA, VIRTEX-5 LXT, 50K, 665FCBGA
ManufacturerXilinx Inc
SeriesVirtex™-5 LXT
XC5VLX50T-1FFG665C datasheets
Product Change Notification
 


Specifications of XC5VLX50T-1FFG665C

No. Of Logic Blocks7200Family TypeVirtex-5
No. Of Speed Grades1Total Ram Bits2211840
No. Of I/o's360Clock ManagementDCM, PLL
I/o Supply Voltage3.3VOperating Frequency Max550MHz
Number Of Logic Elements/cells46080Number Of Labs/clbs3600
Number Of I /o360Voltage - Supply0.95 V ~ 1.05 V
Mounting TypeSurface MountOperating Temperature0°C ~ 85°C
Package / Case665-BBGA, FCBGACore Supply Voltage Range1V
Rohs CompliantYesLead Free Status / RoHS StatusLead free / RoHS Compliant
For Use WithHW-V5-ML561-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML550-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML521-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5GBE-DK-UNI-G - KIT DEV V5 LXT GIGABIT ETHERNET122-1508 - EVALUATION PLATFORM VIRTEX-5Number Of Gates-
Other names122-1565  
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IOB Pad Input/Output/3-State Switching Characteristics
Table 56
summarizes the values of standard-specific data
input delay adjustments, output delays terminating at pads
(based on standard) and 3-state delays.
T
is described as the delay from IOB pad through the
IOPI
input buffer to the I-pin of an IOB pad. The delay varies
depending on the capability of the SelectIO input buffer.
T
is described as the delay from the O pin to the IOB
IOOP
pad through the output buffer of an IOB pad. The delay
varies depending on the capability of the SelectIO output
buffer.
Table 56: IOB Switching Characteristics
I/O Standard
LVDS_25
LVDSEXT_25
HT_25
BLVDS_25
RSDS_25 (point to point)
ULVDS_25
PCI33_3
PCI66_3
PCI-X
GTL
GTLP
HSTL_I
HSTL_II
HSTL_III
HSTL_IV
HSTL_I _18
HSTL_II _18
HSTL_III _18
HSTL_IV_18
SSTL2_I
SSTL2_II
LVTTL, Slow, 2 mA
LVTTL, Slow, 4 mA
LVTTL, Slow, 6 mA
LVTTL, Slow, 8 mA
LVTTL, Slow, 12 mA
LVTTL, Slow, 16 mA
LVTTL, Slow, 24 mA
DS202 (v5.3) May 5, 2010
Product Specification
Virtex-5 FPGA Data Sheet: DC and Switching Characteristics
T
is described as the delay from the T pin to the IOB
IOTP
pad through the output buffer of an IOB pad, when 3-state is
disabled. The delay varies depending on the SelectIO
capability of the output buffer.
Table 57
summarizes the value of T
described as the delay from the T pin to the IOB pad
through the output buffer of an IOB pad, when 3-state is
enabled (i.e., a high impedance state).
T
T
IOPI
Speed Grade
Speed Grade
-3
-2
-1
-3
0.80
0.90
1.06
1.13
1.29
1.01
1.16
1.30
1.17
1.34
0.80
0.90
1.06
1.10
1.26
0.80
0.90
1.06
1.24
1.38
0.80
0.90
1.06
1.13
1.29
0.80
0.90
1.06
1.10
1.27
0.62
0.70
0.82
1.85
2.06
0.62
0.70
0.82
1.85
2.06
0.62
0.70
0.82
1.40
1.56
0.76
0.85
1.00
1.47
1.63
0.76
0.85
1.00
1.51
1.68
0.76
0.85
1.00
1.42
1.57
0.76
0.85
1.00
1.39
1.53
0.76
0.85
1.00
1.44
1.60
0.76
0.85
1.00
1.44
1.60
0.76
0.85
1.00
1.40
1.55
0.76
0.85
1.00
1.36
1.51
0.76
0.85
1.00
1.45
1.61
0.76
0.85
1.00
1.41
1.57
0.76
0.85
1.00
1.48
1.64
0.76
0.85
1.00
1.40
1.55
0.62
0.70
0.82
4.10
4.47
0.62
0.70
0.82
2.87
3.09
0.62
0.70
0.82
2.66
2.91
0.62
0.70
0.82
2.09
2.30
0.62
0.70
0.82
1.94
2.15
0.62
0.70
0.82
1.84
2.04
0.62
0.70
0.82
1.87
2.07
www.xilinx.com
. T
IOTPHZ
IOTPHZ
T
IOOP
IOTP
Speed Grade
-2
-1
-3
-2
1.44
1.13
1.29
1.44
1.49
1.17
1.34
1.49
1.40
1.10
1.26
1.40
1.58
1.24
1.38
1.58
1.44
1.13
1.29
1.44
1.41
1.10
1.27
1.41
2.38
1.85
2.06
2.38
2.38
1.85
2.06
2.38
1.80
1.40
1.56
1.80
1.86
1.47
1.63
1.86
1.93
1.51
1.68
1.93
1.79
1.42
1.57
1.79
1.74
1.39
1.53
1.74
1.85
1.44
1.60
1.85
1.83
1.44
1.60
1.83
1.77
1.40
1.55
1.77
1.72
1.36
1.51
1.72
1.85
1.45
1.61
1.85
1.81
1.41
1.57
1.81
1.87
1.48
1.64
1.87
1.76
1.40
1.55
1.76
5.01
4.10
4.47
5.01
3.41
2.87
3.09
3.41
3.29
2.66
2.91
3.29
2.61
2.09
2.30
2.61
2.46
1.94
2.15
2.46
2.34
1.84
2.04
2.34
2.38
1.87
2.07
2.38
is
Units
-1
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
32